Apple Inc.

Snap Inc.

Yu Chen

Yiwei Ma

Shuo Wu

Tolga Can

Lizhi Zhong

Boon-Aik Ang

Dennis M Fischette, Jr

Meei-Ling Chiang

Samed Maltabas

Shaobo Liu

Vishal Varma

Wenyi Jin

Pyoungwon Park

Joshua Siegel

Litesh Sajnani

Hairong Yu

Gregory N Santos

Richard Y Su

A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.

Analog channel equalization and channel adaptation

A survey distribution system receives a selection of a first subset of a user population. For example, an administrator of the system may select one or more user attributes of the users among the user population. In response, the survey distribution system identified the first subset of users based on the selected attributes. In some example embodiments, the administrator of the system may additionally define a maximum or minimum number of users to be exposed to the content, as well as targeting parameters for the content, such as a period of time in which to distribute the content to the first subset of users, as well as location criteria, such that the content may only be distributed to users located in specific areas.

Survey distribution system

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

Reference clock switching in phase-locked loop circuits

Targeted surveys to a subset of client devices based on geolocation, user application activities, and display duration

Growing community of inventors

Santa Clara, CA, United States of America

Yu Chen