Taiwan Semiconductor Manufacturing Comp. Ltd.

E Ink Holdings Inc.

Prime View International Co. Ltd.

Yu-Chen Hsu

Chen-Shien Chen

Han-Ping Pu

Yao-Chun Chuang

Chi-Ming Wu

Chita Chuang

Chen-Cheng Kuo

Yu-Feng Chen

Hao Chun Liu

Chen-Hua Douglas Yu

Der-Chyang Yeh

Wei-Cheng Wu

Tsung-Shu Lin

Chun-Hung Lin

Meng-Tse Chen

Cheng-Hsien Hsieh

Li-Han Hsu

Guan-Yu Chen

Chien-Chia Chiu

Wei-Chih Lai

Pei-Haw Tsao

Ming Hung Tseng

Hsin-Yu Pan

Hao-Juin Liu

Chuan-Feng Liu

Heng-Hao Chang

Chun-Ta Chien

Chia-Hao Kuo

Ya-Rou Chen

Chih-Chien Chiou

Chi-Meng Wu

Chien-Pang Huang

Cheng-Yi Su

A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Semiconductor package and manufacturing method thereof

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Stress reduction apparatus and method

A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.

Pre-applying supporting materials between bonded package components

An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

Seal rings structures in semiconductor device interconnect layers and methods of forming the same

A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface.

Packages with molding material forming steps

A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees.

Stress reduction apparatus

The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity.

Bump interconnection techniques

An electronic-ink display panel including an active matrix substrate, a front plane laminate and an electronic-ink layer is provided. The active matrix substrate has multiple pixel units. Each pixel unit includes multiple sub-pixel units, and each sub-pixel unit has a storage capacitor. In the same pixel unit, the capacitance of the storage capacitor of at least one sub-pixel unit is different from those of the storage capacitors of the other sub-pixel units. The front plane laminate is disposed above the active matrix substrate and the electronic-ink layer is disposed between the active matrix substrate and the front plane laminate.

Electronic-ink display panel

A display electrode structure and the repairing method thereof are described. The display electrode structure includes a display electrode and at least one opening formed on the display electrode and extending toward the inside of the display electrode so as to easily repair a display electrode defect thereon. The display electrode repairing method uses a laser beam to cut a display electrode from the opening and along the metal line to separate the display electrode from an adjacent display electrode so as to remove a short circuit between the display electrode and the adjacent display electrode.

Repairing method and structure of display electrode

A thin film transistor array substrate suitable for being applied in an electronic ink display device is provided. The thin film transistor array substrate includes a substrate, scan lines, data lines, thin film transistors, pixel electrodes and testing signal lines. The data lines and the scan lines are disposed and define a plurality of pixel regions on the substrate. Each thin film transistor is disposed in the respective pixel region and driven by the corresponding scan line and data line. In addition, each pixel electrode is disposed in respective pixel region and electrically connected to the thin film transistor corresponding thereto. Furthermore, the testing signal line connects to the scan lines and/or the data lines in series. The testing accuracy as well as the production yield of the electronic ink display device and the thin film transistor array substrate can be improved by the design of the aforementioned testing circuit.

Thin film transistor array substrate and electronic ink display device

Growing community of inventors

Hsinchu, Taiwan

Yu-Chen Hsu