Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Chang Jong

Pei-Lun Wang

Hui-Ting Lu

Chia-Cheng Ho

Dah-Chuen Ho

Jian-Hsing Lee

Chien-Chih Chou

Ming-Song Sheu

Jhu-Min Song

Chun-Chien Tsai

Hsueh-Liang Chou

Ming-Ta Lei

Po-Chih Su

Jyun-Guan Jhou

Shun-Liang Hsu

Chien-Shao Tang

Zhe-Yi Wang

Te-Yin Hsia

Alexander Kalnitsky

Ruey-Hsin Liu

Chen-Yi Lee

Shih-Fen Huang

Mohammad Al-Shyoukh

Chen-Bau Wu

You-Kuo Wu

Fei-Yun Chen

Chan-Yu Hung

Lin-Yu Huang

Ming Chyi Liu

Yi-Huan Chen

Chia-Yu Wei

Tsung-Chieh Tsai

Puo-Yu Chiang

Shui-Ming Cheng

Jhih-Bin Chen

Szu-Hsien Liu

Hung-Shu Huang

Liang-Yu Su

Sheng-Fu Hsu

Yuh-Hwa Chang

Yueh-Chiou Lin

Jing-Ying Chen

Hung-Chih Tsai

Huan-Chi Tseng

Tai-Yuan Wu

Chi-Hsuen Chang

Yogendra Yadav

Huan-Chih Yuan

Yu-Lun Lu

Hsiao-Ching Huang

Tsung-chieh Tsai

Hao-Hua Hsu

Hsing-Yi Chien

Ruey-Shin Liu

Hong-Miao Chen

Chang-Tai Yang

Nan-Ying Yang

Pin-Chen Chen

Yi-Kai Ciou

Tun-Yi Ho

Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.

High-voltage semiconductor devices and methods of formation

A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

Semiconductor structure and method of manufacturing the same

A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.

Semiconductor structure and method for forming the same

A semiconductor structure and forming method thereof are provided. A substrate includes a region. A first gate structure and a sacrificial gate structure are recessed in the substrate and disposed in the region. The sacrificial gate structure is adjacent to the first gate structure. A first contact is electrically connected to the first gate structure. A sacrificial gate masking structure is disposed over the sacrificial gate structure. An upper surface of the sacrificial gate structure is entirely covered by the sacrificial gate masking structure.

Semiconductor structure and forming method thereof

Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Checkerboard dummy design for epitaxial open ratio

Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate structure overlies a substrate between a source region and a drain region. A drift region is disposed laterally between the gate structure and the drain region. A first dielectric layer overlies the substrate. A field plate is disposed within the first dielectric layer between the gate structure and the drain region. A conductive wire overlies the first dielectric layer and contacts the field plate. At least a portion of the conductive wire directly overlies a first sidewall of the drift region.

Field plate structure to enhance transistor breakdown voltage

Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

Field plate structure for high voltage device

The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Strained transistor with conductive plate

A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Strap technology to improve ESD HBM performance

An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Avalanche-protected transistors using a bottom breakdown current path and methods of forming the same

A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Methods for forming integrated circuit having guard rings

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a gate structure over a substrate and between a source region and a drain region. A composite etch stop structure is formed over the gate structure and a first inter-level dielectric (ILD) layer is formed over the composite etch stop structure. The composite etch stop structure has a plurality of stacked dielectric materials. The first ILD layer is etched to concurrently define contact openings extending to the substrate and a field plate opening extending to the composite etch stop structure. The contact openings and the field plate opening are concurrently filled with one or more conductive materials.

Composite etch stop layer for contact field plate etching

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Hsinchu, Taiwan

Yu-Chang Jong