Advanced Semiconductor Engineering, Inc.

Yu-Chang Chen

Hao-Chih Hsieh

Tun-Ching Pi

Sung-Hung Chiang

Chang-Lin Yeh

Chin-Li Kao

Tang-Yuan Chen

Meng-Kai Shih

Jin-Feng Yang

Bo-Syun Chen

A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Semiconductor device package

A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.

A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.

Semiconductor device package and method of manufacturing the same

Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same

A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.

Semiconductor package structure and method for manufacturing the same

A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

A semiconductor package device includes a substrate, an electronic component disposed on the substrate, and a package body. The electronic component has a first surface adjacent to the substrate and a second surface opposite to the first surface. The second surface has at least five edges, and the package body encapsulates the electronic component and exposes the second surface of the electronic component.

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Kaohsiung, Taiwan

Yu-Chang Chen