Rambus Inc.

Apple Inc.

Nvidia Corporation

Yu Chang

Kyung Suk Oh

Lei Luo

Huabo Chen

Huy M Nguyen

Cristian Gozzi

Mitesh D Katakwar

Michael Hopgood

Hakki Ozguc

Xuchen Zhang

Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

Reflection cancellation for single-ended signaling

A transceiver circuit having a T-coil circuit, inductive termination, and an equalization circuit is disclosed. The transceiver includes a transmitter having an output coupled to a first node, and a receiver having an input coupled to the first node. A T-coil circuit is coupled between the first node and an input/output (I/O) node. The T-coil circuit includes first and second inductors coupled in series between the first node and the I/O node, the inductors being coupled at a second node. A termination circuit is coupled between the first node and a reference node, the termination circuit including a third inductor. The transceiver circuit also includes an equalization circuit configured to convey an equalization signal to the second node.

Transceiver circuit having T-coil, inductive termination, and equalization

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Changing settings for a transient period associated with a deterministic event

Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.

Clock data recovery circuit

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

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Los Altos, CA, United States of America

Yu Chang