Hrl Laboratories, LLC

Yu Cao

Rongming Chu

Danny M Kim

Thaddeus D Ladd

Zijian Ray Li

Adam J Williams

Zijian “Ray” Li

Mary Y Chen

Zijian "Ray" Li

A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.

Doped gate dielectrics materials

Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

In situ fabrication of horizontal nanowires and device using same

A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.

Digital alloy based back barrier for P-channel nitride transistors

Semiconductor device having in situ formed horizontal nanowire structure

Doped gate dielectric materials

Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p&#x2212;GaN material on a n&#x2212;GaN vertical surface extending vertically from an n&#x2212;GaN horizontal surface on an n&#x2212;GaN drift layer to form a first PN junction, wherein the n&#x2212;GaN horizontal surface extends horizontally from the n&#x2212;GaN vertical surface and the n&#x2212;GaN horizontal surface has a layer of dielectric material formed on the n&#x2212;GaN horizontal surface that extends from the p&#x2212;GaN surface.

Lateral GaN PN junction diode enabled by sidewall regrowth

A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

Tunnel barrier schottky

A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.

III-nitride P-channel transistor

A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer.

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Agoura Hills, CA, United States of America

Yu Cao