Skhynix Inc.

Seagate Technology Incorporated

Sk Hynix Memory Solutions Inc.

Lsi Corporation

Yu Cai

Fan Zhang

Aman Bhatia

Chenrong Xiong

Naveen Kumar

Erich Franz Haratsch

Yunxiang Wu

June Lee

Zhengang Chen

Xuanxuan Lu

Ning Chen

David J Pignatelli

Haibo Li

HyungSeok Kim

Abhiram Prabahkar

Earl T Cohen

Yi-Min Lin

Kyoung Lae Cho

Soo Jin Kim

Ivana Djurdjevic

Abhiram Prabhakar

Zhimin Dong

Lingqi Zeng

Abdelhakim Alhussien

Johnson Yen

Timothy Lawrence Canepa

Yue Li

Abdel-Hakim S Alhussien

Ngok Ying Chu

Taeil Um

Norton Chu

Jun Feng

Sangcheol Lee

Shi Yin

Jaesung Sim

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Data storage device

Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.

Storage device performance optimization using deep learning

A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.

Memory system and method for read operation based on grouping of word lines

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Soft chip-kill recovery for multiple wordlines failure

A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.

Media quality aware ECC decoding method selection to reduce data access latency

Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

Memory system to process multiple word line failures with limited storage and method of operating such memory system

Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Soft chipkill recovery for bitline failures

Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.

Decoder for memory system and method thereof

Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.

Neighbor assisted correction error recovery for memory system and method thereof

Encoders and decoders are provided for memory systems. An encoder scrambles data bits corresponding to a logical page, selected from among multiple logical pages, using a plurality of random sequences, to generate a plurality of scrambled sequences; selects, as an encoded sequence, a scrambled sequence among the plurality of scrambled sequences; and provides a memory device with the encoded sequence to store the encoded sequence in multiple level cells. The selected scrambled sequence has the lowest number of logical high values among the plurality of scrambled sequences.

Encoder and decoder for memory system and method thereof

Devices and methods that generate code on chip-kill parity in which the code is generated and shortened using variable node degree information for improved decoding of data. In one aspect, memory controller comprises an encoder configured to construct a first code of D data bits and P parity bits, determine the number of distinct variable degree nodes L and the number of data bits of each of the variable degree nodes in the first code, and construct a second code that is shorter than the first code based on the determined number of variable degree nodes and the number of data bits of each of the variable degree nodes in the first code.

Memory system with super chip-kill recovery and method of operating such memory system

Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.

Memory system with deep learning based interference correction capability and method of operating such memory system

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San Jose, CA, United States of America

Yu Cai