Marvell International Limited

Intel Corporation

Yu Bai

Premanand Sakarda

Qinwei Gu

Kermin ChoFleming

Priya N Vaidya

Marlon Moncrieffe

Bryan C Morgan

Scott B Peirce

Simon C Steely, Jr

Ping Zou

Simon C Steely Jr

An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.

Multi-stage cache tag with first stage tag size reduction

Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.

Simulated-annealing based memory allocations

Systems, methods, and apparatuses relating to memory interface circuit allocation in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for an improved memory sub-system design via the improvements to allocation discussed herein.

Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator

Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.

Method and apparatus for selecting an operating frequency of a central processing unit, based on determining a millions of instruction per second (MIPS) value associated with the central processing unit

Systems, methods, and other embodiments associated with a low power audio codec are described. According to one embodiment, an audio codec includes an audio buffer configured to store decoded audio data received from an application processor external to the audio codec. The application processor is configured to decode audio data in a RUN mode. The audio codec is configured to store, in the audio buffer, decoded audio data received from the application processor when the application processor is in IDLE mode and provide the stored decoded audio data to an audio device while the application processor is in a low power mode.

Audio codec with audio buffer to store decoded audio data wherein decoding processor enters low power mode during playback

Some of the embodiments of the present disclosure provide a method comprising generating a plurality of power profiles for a corresponding plurality of processing cores, wherein each power profile of the plurality of power profiles includes power consumptions of a corresponding processing core under various operating conditions; generating a plurality of candidate configurations, wherein each candidate configuration comprises corresponding candidate operating conditions for the plurality of processing cores; and based at least in part on the plurality of power profiles, selecting a first candidate configuration of the plurality of candidate configurations for managing the plurality of processing cores. Other embodiments are also described and claimed.

System and method for selecting a power management configuration in a multi-core environment to balance current load demand and required power consumption

Systems, methods, and other embodiments associated with a low power audio codec are described. According to one embodiment, an apparatus includes an audio codec having an audio buffer configured to store decoded audio data received from a processor. The audio codec is configured to provide the stored decoded audio data to an audio device while decoded audio data is not being received from the processor. According to another embodiment, a method includes receiving a request for decoded audio data from an audio codec with an audio buffer, entering a RUN mode and providing decoded audio data stored in processor memory to the audio codec for storage in the audio buffer. After receiving a buffer full signal from the audio codec the method includes entering a low power mode while the audio codec provides an audio signal to an audio device.

Low power audio codec

Millions of instruction per second (MIPS) based idle profiler in a power management framework

System and method for selecting a power management configuration in a multi-core environment according to various operating conditions such as voltage, frequency, power mode, and utilization factor varied on a per-core basis

Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

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Shrewsbury, MA, United States of America

Yu Bai