Fujitsu Corporation

Pfu Limited

Yozo Nakayama

Hirohide Sugahara

Akira Kabemoto

Toshiyuki Muta

Takatsugu Sasaki

Takayuki Shimamura

Jun Sakurai

Junji Nishioka

Satoshi Shinohara

Naohiro Shibata

Takeshi Horie

Rajarshi Mukherjee

Toshiyuki Shimizu

Haruhiko Ueno

Hiroaki Ishihata

Toshiya Mima

A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the states, and the test element is applied to a design-under-test. Data flow information, determined while applying the test element to the design-under-test, is store in a transaction database, and the data items read and modified by the data flow information are stored in a data database. At least one result is determined based on the application of the test element to the design-under-test.

Method and system for design verification and debugging of a complex computing system

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Multiprocessor, memory accessing method for multiprocessor, transmitter

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Coherence apparatus for cache of multiprocessor

Interruption handling system

Growing community of inventors

Kahoku-gun, Japan

Yozo Nakayama