Altera Corporation

Advanced Micro Devices Corporation

Yow-Juang W Liu

Bruce B Pedersen

Irfan Rahim

Peter John McElheny

David Lewis

Vaughn Betz

Minchang Liang

Richard G Cliff

Hugh Sungki O

Jian Feng Chen

Peter Mcelheny

Gu Fung David Tsuei

A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Apparatus and methods for adjusting performance of integrated circuits

An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Apparatus and methods for multi-gate silicon-on-insulator transistors

A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Apparatus and methods for adjusting performance of programmable logic devices

An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.

Integrated circuits with reduced standby power consumption

A method for manufacturing a non-volatile memory device, the device having a core memory cell region and a periphery region, comprising the steps of: forming memory cell gate structures in the core memory cell region; forming active regions adjacent to the gate structure through a blanket implant; forming an implant/etch mask; implanting an impurity into one of the active regions; etching an oxide layer in the implant region; and forming active devices in the periphery region. In a further aspect, the method comprises method of performing a self aligned source etch in forming a memory device, comprising: forming resist spacers adjacent to the channel regions of the memory device; and etching the oxide layer.

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San Jose, CA, United States of America

Yow-Juang W Liu