Yangtze Memory Technologies Co., Ltd.

Youxin He

Xiaojiang Guo

Feifei Zhu

Jong Hoon Kang

Xianwu Luo

Jiangwei Shi

Qi Hu

Ruiyang Zhang

The present disclosure discloses an electronic device, a memory system and a power control method, which belong to the field of storage technology. A disclosed electronic device can comprise a host and a memory system. The host can comprise a power management unit, and a first interface configured to send an identifier indicating a peak power capability supported by the power management unit. The memory system can comprise at least one memory device coupled with the host, a second interface communicated with the first interface and configured to receive the identifier, and a memory controller coupled the memory device and configured to determine a peak power management policy matches the peak power capability according to the identifier.

Electronic devices and memory systems having a power control function, and power control methods

In certain aspects, a method for operating a memory controller is disclosed. The method includes determining a total used amount of a user data storage space of a memory device. The method also includes determining whether a garbage collection (GC) triggering condition is satisfied based on the total used amount of the user data storage space. The method further includes determining whether to perform a GC process on the memory device based on whether the GC triggering condition is satisfied.

Memory controller performing garbage collection, memory system, method, and storage medium thereof

Methods, systems, and apparatus for management of operations in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a first buffer, a second buffer, and a third buffer including a plurality of data buffers. The memory device receives a first portion of first data of a first request from the memory controller, and stores the first portion of the first data in the first buffer or a first data buffer of the third buffer. The memory controller sends a second request to the memory device. The memory device, in response to the second request, moves the first portion of the first data from the first buffer or the first data buffer to the second buffer. The memory device performs an operation in response to the second request without using the second buffer.

Managing operations in memory systems

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Open block-based read offset compensation in read operation of memory device

The present disclosure provides a method for programing flash memory devices. The method may include programming a selected page of the NAND flash memory device according to programming data. The selected page may include memory cells corresponding to a word line. The programming of the selected page may include programming operations with programming voltages applied on the word line and a read operation performed on the selected page.

Double program debug method for NAND memory using self-verification by internal firmware

The present disclosure provides a method of data protection for a NAND memory. The method includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of the first and second pages includes a plurality of programming operations using a plurality of programming voltages and a plurality of verifying operations to determine whether programmed memory cells of the first page have threshold voltage levels according to the programming data. The method also includes determining a completion of the programming of the first and second pages based on each of the plurality of verification operations returning a pass result. The method also includes performing, after the determining, a read operation on the second page by the NAND flash memory device to self-verify the data stored at the second page.

Redundant data protection for NAND memory using self-verification by internal firmware

In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)word line and iRAID parity data to obtain (i+1)RAID parity data, and store the (i+1)RAID parity data in the parity buffer space, the (i+1)RAID parity data overwriting the iRAID parity data, i being a positive integer greater than or equal to 1.

Memory systems and operating methods thereof

In certain aspects, a memory system may include at least one memory device and a memory controller coupled to the at least one memory device. Each memory device may include an array of memory cells and a control logic coupled to the array of memory cells. The memory controller and the control logic of the memory device may be powered by a first power source having a first predetermined power consumption threshold. The array of memory cells of the memory device may be powered by a second power source having a second predetermined power consumption threshold. The memory controller may be configured to maintain a first queue of memory operations, wherein execution of the memory operations in the first queue causes power consumption from the first power source; maintain a second queue of memory operations, wherein execution of the memory operations in the second queue causes power consumption from the second power source; separately determine whether execution of subsequent memory operations in the first and second queues, respectively, would cause the corresponding first and second power sources to be overloaded; execute, based on the determination, the subsequent memory operation in the first or second queue that would not cause the corresponding first or second power source to be overloaded; and delay, based on the determination, the subsequent memory operation in the first or second queue that would cause the corresponding first or second power source to be overloaded.

Power management for a memory system

In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.

The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.

Data protection in NAND memory using internal firmware to perform self-verification

The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data. The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

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Hubei, China

Youxin He