Applied Materials, Inc.

Applied Materials Israel Limited

Youval Nehmadi

Vicky Svidenko

Rinat Shimshi

Alexander T Schwarm

Ariel Ben-Porath

Sundar Jawaharlal

Ofer Bokobza

Jacob Joseph Orbon, Jr

Zamir Abraham

Erez Ravid

Gilad Almogy

Ovadya Menadeva

Yair Eran

Yaron Cohen

Sergey Latinsky

Gil Sod-Moriah

Chen Ofek

Josephine Phua

Evgeny Levin

Orit Afek

Jacob J Orbon, Jr

Sundar Jawaharlah

Rinat Shishi

Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.

Method and apparatus for determining factors for design consideration in yield analysis

In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.

Inline defect analysis for sampling and SPC

In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.

Stage yield prediction

In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.

Dynamic inline yield analysis and prediction of a defect limited yield using inline inspection defects

A system software product and a method for evaluating a mask, the method including the stages of: defining multiple CD measurement target windows; defining multiple pattern recognition windows such that the multiple CD measurements windows do not overlap the multiple pattern recognition windows, wherein each CD measurement target window and an associated pattern recognition window are positioned within a measurement area that is scannable without introducing a substantial mechanical movement; performing multiple critical dimension measurements of multiple patterns of an object being manufactured by exposing the mask to radiation, wherein the performing comprises using at least one CD measurement target window and at least one pattern recognition window; and evaluating the mask.

System, method and computer software product for inspecting charged particle responsive resist

Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

Design-based method for grouping systematic defects in lithography pattern writing system

Grouping systematic defects with feedback from electrical inspection

The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing the received design information to provide a large number of measurement targets; and (iii) associating target measurement parameters to each of large number of measurement targets. The invention provides a system that includes: (i) an interface for receiving design information representative of a portion of a layer of an object that includes sub micron measurement targets; and (ii) a processor, coupled to the interface, for processing the received design information to provide a large number of measurement targets; and for associating target measurement parameters to each of large number of measurement targets.

Process monitoring system and method for processing a large number of sub-micron measurement targets

A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.

Design-based monitoring

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Modiin, Israel

Youval Nehmadi