Hitachi, Ltd.

Hitachi Software Engineering Company, Ltd.

Hitachi Information Technology Co., Ltd.

Yousuke Nagao

Tetsuo Sasaki

Katsuyoshi Suzuki

Tatsuki Ishii

Hachidai Nagase

Itaru Matsumoto

Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.

Design method and system for achieving a minimum machine cycle for semiconductor integrated circuits

A method and a system for assisting mending of an LSI after it has been formed into a chip which is necessitated by modification of logic etc. The mending includes corrections by connecting or cutting interconnections of the LSI. The assisting method and system provides a method and a system for detecting which interconnection or connections should be subjected to mending according to the logic modification, or a method and a system for detecting an area or areas where the intended mending can be carried out, or a method and a system for advising a mending-allowable rate of the LSI. This invention further provides a wiring structure suited for mending of the LSI and a wiring method for the same. By this method, a wiring structure which preliminarily has a mending area in preparation for possible modification in logic is produced.

Method and a system for assisting mending of a semiconductor integrated

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Hadano, Japan

Yousuke Nagao