Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Toshiba Electronic Devices & Storage Corporation

Yousuke Hagiwara

Ichiro Seto

Shigehito Saigusa

Yuki Fujimura

Kenta Shibasaki

Yasuhiro Hirashima

Toshiyuki Yamagishi

Mitsuyuki Ashida

Yumi Takada

Hiroyuki Kobayashi

Satoshi Inoue

Atsuhiro Kinoshita

Takao Marukame

Akio Sugahara

Jun Deguchi

Hiroshi Yoshida

Shouhei Kousai

Toshiya Mitomo

Tetsuya Fujita

Takeshi Hioka

Kensuke Yamamoto

Masamichi Suzuki

Dai Nakamura

Kei Shiraishi

Shigeki Nagasaka

Yoshihiko Shindo

A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

Memory system

A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.

Semiconductor memory device

According to one embodiment, a detection circuit includes a first filter circuit configured to output a first voltage, a ramp circuit configured to output a ramp voltage, a comparator configured to output a first result of comparison between the first voltage and the ramp voltage and a second result of comparison between a second voltage and the ramp voltage, and a controller, wherein the controller determines a first period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the first voltage and the ramp voltage is inverted, and determines a second period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the second voltage and the ramp voltage is inverted.

Detection circuit, semiconductor memory device, memory system

In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

Output circuit

A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.

Semiconductor storage device and memory system

According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.

A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fto a transmitter and up-converting the test signal with a frequency fand down-converting with the frequency f. A frequency 2fcomponent is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fcomponent in the test signal.

Carrier leakage correction method for quadrature modulator

According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.

Communication device and orthogonal error measurement method for communication device

A transmission and reception circuit includes a transmission circuit, a reception circuit, and a signal feedback path. The transmission path includes an output section, a signal generating circuit generating an in-phase component signal and an orthogonal component signal, and a transmission analog baseband circuit configured to perform digital to analog conversion of the generated in-phase component signal and orthogonal component signal. The reception circuit includes an input section, a reception analog baseband circuit performing analog to digital conversion of the transmitted in-phase component signal and orthogonal component signal, and a signal detection circuit that detects the analog-to-digital converted in-phase component signal and orthogonal component signal converted by the reception analog baseband circuit. The signal feedback path has a first end which is connected to the output section of the transmission circuit, and a second end which is connected to the input section of the reception circuit.

Transmission and reception circuit, transceiver, and method of correcting time difference of signal

A quadrature demodulator includes a quadrature demodulating circuit configured to generate an analog in-phase signal and an analog quadrature signal based on an output signal of a low noise amplifier, and a controller configured to cause a thermal noise, instead of the output signal of the low noise amplifier, to be input to the quadrature demodulating circuit, when a correction parameter to correct a mismatch between the in-phase and quadrature signals is being calibrated.

Quadrature demodulator and wireless receiver

In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n&#x3e;1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n&#x2212;1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.

DA converter and wireless communication apparatus

A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.

Growing community of inventors

Kawasaki Kanagawa, Japan

Yousuke Hagiwara