Microsoft Technology Licensing, LLC

Youssef M Barakat

Arun Upadhyaya Kishan

Tristan Anthony Brown

Jason Stewart Wohlgemuth

Pedro Miguel Sequeira De Justo Teixeira

Omid Fatemieh

Ten H Tzen

Max Alan McMullen

Marcus J Andrews

Terry Jack Mahaffey

Ameet Arun Chitre

Andrew Raffman

Henry Morgan

Sameer Avinash Nene

YongKang Zhu

Minsang Kim

Christopher Martin McKinsey

Mehmet Iyigun

Yevgeniy Bak

Jon Robert Berry

Neeraj Kumar Singh

Karthick Krishnamoorthy

Kinshuman Kinshumann

Rogerio Ramos

Balaji Krishnamachari-Sampath

Murali Ravirala

Gabriel Knezek

Brian Perkins

Jinsub Moon

Clarence Dang

Jeremiah S Samli

Shirish Gajera

Methods, systems, apparatuses, and computer program products are provided for coordinating a distributed database transaction. A transaction driver, such as a client machine, may initiate a distributed transaction. The transaction driver may transmit to a transaction coordinator a driver report that includes identifying information related to the distributed transaction, including an identification of participants involved in the transaction. The coordinator may determine whether participant reports, which include a status of the portion of the distributed database transaction of a particular participant, are received from each of the participants. Participant reports may also identify participants that are descendants of the reporting participant. The transaction coordinator may store, in a table, information to track the progress of the distributed transaction. Using the table, an outcome of the distributed transaction may be determined and transmitted to one or more of the involved participants.

Lock free distributed transaction coordinator for in-memory database participants

During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.

Memory ordering annotations for binary emulation

A system for updating a file and resolving conflict in updating of the file in a distributed file store is disclosed. The system includes a receiver, an updater, and a conflict detector. The receiver receives the file formed of a plurality of extents to be updated. An extent is indicative of a piece of data content of the file and formed of a plurality of packets of substantially equal size. The receiver further receives instructions indicative of one or more extents of the file in which the updates are to be made. The updater updates one or more packets, based on the instructions. The conflict detector detects that a portion of the file is being currently updated, receives a request to update the same portion from another application, and decline the request by the other application to update the same portion to resolve the conflict.

Updateable distributed file framework

A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.

Tracking work between system entities

An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. These assignments can be changed given current operating conditions of the system.

Operating system-managed interrupt steering in multiprocessor systems

Constructs to define a Trusted Execution Environment Driver that can implement a standard communication interface in a first environment for discovering and/or exchanging messages with secure applications/services executed in a Trusted Execution Environment (TrEE). The first environment can represent an environment with a different security policy from the TrEE. The TrEE driver can include a standard interface and/or mechanism by which applications/services and drivers within a first environment can access secure applications/services in the TrEE, a standard interface and/or mechanism by which third-party vendors can expose their TrEE applications/services to a first environment, a standard interface and/or mechanism by which a TrEE can request applications/services, on its own behalf, from the first environment, and a standard interface and/or mechanism to facilitate the management of secure application/services and/or provide I/O prioritization and security protection for individual secure applications/services.

Trusted execution environment extensible computing device interface

Various systems and methods for translating atomic read-modify-write accesses are described herein. In one example, a method includes determining that a machine instruction of a first language specifies an atomic read-modify-write access. The method includes generating machine instructions of the second language to perform an atomic access for the address if the address is aligned. The method includes generating machine instructions of a second language to acquire a global lock if the address is unaligned. Additionally, the method includes generating machine instructions of the second language to perform a non-atomic access for the address if the address is unaligned. Also, the method includes generating machine instructions of the second language to release the global lock if the address is unaligned.

Translating atomic read-modify-write accesses

Heterogeneous thread scheduling techniques are described in which a processing workload is distributed to heterogeneous processing cores of a processing system. The heterogeneous thread scheduling may be implemented based upon a combination of periodic assessments of system-wide power management considerations used to control states of the processing cores and higher frequency thread-by-thread placement decisions that are made in accordance with thread specific policies. In one or more implementations, a system workload context is periodically analyzed for a processing system having heterogeneous cores including power efficient cores and performance oriented cores. Based on the periodic analysis, cores states are set for some of the heterogeneous cores to control activation of the power efficient cores and performance oriented cores for thread scheduling. Then, individual threads are scheduled in dependence upon the core states to allocate the individual threads between active cores of the heterogeneous cores on a per-thread basis.

Heterogeneous thread scheduling

An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. On a regular basis, these assignments can be changed given current operating conditions of the system.

Systems and methods for debouncing a signal line within a computer device are provided. The mechanical nature of physical buttons and switches oftentimes present irregular or noisy signals on a signal line when depressed by a user. Thus, noise and/or irregular waveforms may be present on a signal line that is monitored to produce interrupt signals, when deemed valid and genuine. In many embodiments given herein, debounce modules and techniques set a debounce interval timer and/or a noise filtering interval timer in which debounce modules and/or techniques may note whether the signal line is still asserted (e.g., possibly a genuine interrupt signal) during the debounce interval timer and stable (e.g., no further interrupts have fired) during the noise filtering interval timer.

Software debouncing and noise filtering modules for interrupts

Systems and methods for rebootless updating of a IHV display driver are disclosed. According to such a method, first, the operating system stops the driver from running Second, the system switches over to an interim or temporary display driver, which be a default driver provided with the operating system. Third, the new hardware-specific driver is started. Thus, a hardware-specific display driver may be updated without rebooting.

Rebootless display driver upgrades

Systems and methods for rebootless updating of a IHV display driver are disclosed. According to such a method, first, the operating system stops the driver from running. Second, the system switches over to an interim or temporary display driver, which be a default driver provided with the operating system. Third, the new hardware-specific driver is started. Thus, a hardware-specific display driver may be updated without rebooting.

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Redmond, WA, United States of America

Youssef M Barakat