International Business Machines Corporation

Youri V Tretiakov

Richard Paul Volant

Robert Allen Groves

Anil Kumar Chinthakindi

David Goren

Kunal Vaed

Rachel Gordin

Kurt Alan Tallman

Sue Ellen Strang

John Katzenstein

A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

Layout determining for wide wire on-chip interconnect lines

A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Suspended transmission line structures in back end of line processing

A method for detemiining fringing capacitances on passive devices within an integrated circuit is disclosed. A fringing capacitance region on a passive device is initially divided into a group of fringing electric field areas. A set of fringing capacitance equations is then developed for the fringing electric field areas accordingly. A determination is made as to whether or not an accuracy of the fringing capacitance equations meets a predetermined threshold. If so, then the fringing capacitance equations are utilized in compact device models to determine fringing capacitance on the passive device; otherwise, the physically-based fringing capacitance equations are fitted to a set of extracted data to generate a refined set of physically-based fringing capacitance equations, and the refined set of physically-based fringing capacitance equations is utilized in compact device models to determine fringing capacitance on the passive device.

Method for determining fringing capacitances on passive devices within an integrated circuit

Method of forming suspended transmission line structures in back end of line processing

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South Burlington, VT, United States of America

Youri V Tretiakov