Samsung Electronics Co., Ltd.

Younwoong Chung

Sungjun Kim

Jongshin Shin

Han-Kyul Lim

Donguk Park

Dongho Choi

Gyeonghan Cha

Yungeun Nam

Chaeryung Kim

JungMyung Choi

Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.

Transceiver performing internal loopback test and operation method thereof

An electronic circuit receives transmission signals from three or more communication lines. The electronic circuit includes a clock-data recovery circuit and a control value generation circuit. The clock-data recovery circuit outputs a recovered clock based on a transition generated in reception signals. The clock-data recovery circuit outputs recovered signals based on the recovered clock and the reception signals. The recovered clock has a first edge in response to the transition generated in the reception signals. The recovered clock has a second edge in response to a reset signal generated based on a delay of the recovered clock. The delay of the recovered clock is adjusted based on a control value provided from the control value generation circuit. The control value is adjusted based on change of a communication condition.

Electronic circuit adjusting delay depending on communication condition

A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Skew calibration circuit and operation method of the skew calibration circuit

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Seongnam-si, South Korea

Younwoong Chung