Samsung Electronics Co., Ltd.

Younho Jeon

Jeongho Lee

Hyeokjun Choe

Younggeon Yoo

Ipoom Jeong

Wonseb Jeong

Heehyun Nam

Hee Hyun Nam

Jaeho Shin

Hyodeok Shin

Youngjin Cho

Chanho Yoon

Hyo-Deok Shin

JeongHo Lee

Daehui Kim

A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

Memory controller performing selective and parallel error correction, system including the same and operating method of memory device

A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.

System, device, and method for accessing memory based on multi-protocol

A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

System, device and method for accessing device-attached memory

An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

Interface circuit for providing extension packet and processor including the same

A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

Storage system and method to perform workload associated with a host

A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.

System, device and method for indirect addressing

A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.

Growing community of inventors

Gimhae-si, South Korea

Younho Jeon