Samsung Electronics Co., Ltd.

Youngtek Oh

Insu Jeon

Wontaek Seo

Jinwook Jung

Hyeokshin Kwon

Minhyun Lee

Taein Kim

Seunggeol Nam

Gukhyon Yon

Hyeonjin Shin

Joonyong Park

Dongho Kim

Kyungwook Hwang

Changseok Lee

Sanghoon Song

Boreum Jeong

Hwansoo Suh

Junsik Hwang

Moonil Jung

Minchul Yu

Yunju Yu

Hyeyoung Kwon

A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×10cmto about 10×10cm, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

Vertical NAND flash memory device and method of manufacturing the same

A semiconductor chip wet transfer method includes: preparing a transfer substrate that includes a plurality of recesses; supplying a liquid that includes semiconductor chips onto the plurality of recesses of the transfer substrate; aligning the semiconductor chips in the plurality of recesses by sweeping, with an align bar, an upper surface of the transfer substrate supplied with the liquid; and performing cleaning by removing semiconductor chips that are not aligned in the plurality of recesses by using a first magnetic force generating device disposed facing a lower surface of the transfer substrate.

Chip wet transfer method and equipment using magnetic force

Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

Vertical nonvolatile memory device including memory cell string

A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

Nonvolatile memory device and apparatus including the same

Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

Transistor including electride electrode

Provided is a sound source tracking apparatuses including a vibration unit including vibrators configured to vibrate in response to an ambient sound, the ambient sound including individual sounds, and a processor configured to separate the ambient sound into individual sounds, to determine a target individual sound having a target tone color among the individual sounds, and to obtain a relative location of a target sound source that generates the target individual sound.

Apparatus for tracking sound source, method of tracking sound source, and apparatus for tracking acquaintance

A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

Silicene electronic device

Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.

Method of forming nanostructure, method of manufacturing semiconductor device using the same, and semiconductor device including nanostructure

Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.

Multi-qubit device and quantum computer including the same

Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a 2-dimensional honeycomb structure formed as one of a monolayer and a double layer. The silicene material layer includes a doping region doped with at least one material from the group of Group 1, Group 2, Group 16 and Group 17 and at least one of a p-type dopant or an n-type dopant.

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Suwon-si, South Korea

Youngtek Oh