Samsung Electronics Co., Ltd.

Youngsun Song

Kitae Park

Sangyong Yoon

Ohsuk Kwon

BoGeun Kim

Seung-Hwan Shin

Hyun-Wook Wook Park

Ki Tae Park

Jaeyong Jeong

Hyunggon Kim

Jung-Soo Kim

Sooyeol Yang

A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.

Negative level shifters and nonvolatile memory devices including the same

In a method of writing data in a memory device, a plurality of duplicated bit rows is generated by performing a first duplication operation in which a plurality of bits included in write data are copied by units of bits. A plurality of duplicated bit groups is generated by performing a second duplication operation in which the plurality of duplicated bit rows is copied by units of rows. The plurality of duplicated bit groups is stored into a plurality of memory regions included in the memory device, respectively. Each of the plurality of memory regions is a region that is simultaneously sensed during a data read operation.

Method of writing data in memory device, method of reading data from memory device and method of operating memory device including the same

In a processing in memory (PIM) method using a memory device, m*n multiplicand arrangement bits are stored in m*n memory cells by copying and arranging m multiplicand bits of a multiplicand value and m*n multiplier arrangement bits are stored in m*n read-write unit circuits corresponding to the m*n memory cells by copying and arranging n multiplier bits of a multiplier value. The m*n multiplicand arrangement bits stored in the m*n memory cells are selectively read based on the m*n multiplier arrangement bits stored in the m*n read-write unit circuits, and m*n multiplication bits are stored in the m*n read-write unit circuits based on the selectively read m*n multiplicand arrangement bits. A multiplication value of the multiplicand value and the multiplier value is determined based on the m*n multiplication bits stored in the m*n read-write unit circuits.

Method of processing in memory (PIM) using memory device and memory device performing the same

A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.

Storage device and related programming method

A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Nonvolatile memory devices and methods of programming nonvolatile memory devices

A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented.

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Yongin-si, South Korea

Youngsun Song