Skhynix Inc.

Korea Advanced Institute of Science and Technology

Youngsuk Moon

Wongyu Shin

Leesup Kim

Yongkee Kwon

Jaemin Jang

Youngjae Jin

A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

Memory device supporting rank-level parallelism and memory system including the same

A semiconductor memory device includes a cell circuit including a plurality of cell dies arranged in a cell die stack. The semiconductor device also includes a control circuit configured to control the cell circuit, wherein the control circuit includes an address decoder and an address conversion circuit. The address decoder is configured to decode an address signal provided by a host and to output address information including a first address which identifies a first cell die, of the plurality of cell dies, requested by the host. The address conversion circuit is configured to convert the first address to a second address using the address information and to provide the second address to the cell circuit, wherein the second address is used to identify a second cell die of the plurality of cell dies different from the first cell die.

Semiconductor memory device for controlling an address for temperature management

Growing community of inventors

Yongin, South Korea

Youngsuk Moon