Samsung Electronics Co., Ltd.

Youngnam Hwang

Ihor Vasyltsov

Seungwook Lee

Yongha Park

Myung Jin Kang

Hyungdal Kwon

Jaewon Yang

Jinmin Kim

Yong Kwan Kim

Jung-In Kim

Wooseok Chang

Hyunsik Park

Changyong Um

A neuromorphic computing device includes a first memory cell array comprising a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines; a second memory cell array comprising a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line; a current-to-voltage converting circuit configured to output a plurality of signal voltages respectively corresponding to the plurality of read currents and output at least one reference voltage corresponding to the at least one reference current; and an analog-to-digital converting circuit configured to convert the plurality of signal voltages to a plurality of digital signals using the at least one reference voltage and output the plurality of digital signals.

Neuromorphic computing device and operating method thereof

A neuromorphic computing device a method of controlling thereof are provided. The neuromorphic computing device includes a first memory cell array including resistive memory cells that are connected to wordlines, bitlines and source lines, and configured to store data and generate read currents based on input signals and the data; a second memory cell array including reference resistive memory cells that are connected to reference wordlines, reference bitlines and reference source lines, and configured to generate reference currents; and an analog-to-digital converting circuit configured to convert the read currents into digital signals based on the reference currents, wherein a voltage is applied to the reference wordlines, the reference resistive memory cells are arranged in columns to form reference columns, and the reference columns are configured to generate column currents, and one of the reference currents is generated by averaging at least two of the column currents.

Neuromorphic computing device and method of operating the same

A memory device including a three-dimensional racetrack and an operating method of the memory device are provided. The memory device includes a first racetrack, a first transistor, a first domain index controller, a bit line driver, a plurality of first magnetic tunnel junction (MTJ) elements, a plurality of first cell transistors, and a source line driver.

Memory device including three-dimensional racetrack and operating method thereof

A semiconductor device includes memory cells connected to word lines, bit lines, and one source line, a row decoder connected to the word lines, and a sense amplifier circuit connected to the bit lines. In a program operation for two or more selected memory cells, a reference voltage is applied to the one source line, the sense amplifier circuit inputs a selected voltage to one selected bit line connected to the selected memory cells, and the row decoder inputs, to selected word lines connected to respective ones of the selected memory cells, a first program voltage lower than the reference voltage or a second program voltage higher than the reference voltage. Each of the memory cells includes a ferroelectric layer in which at least one of a polarization direction and a polarization degree changes depending on a voltage input to each of the word lines.

Semiconductor device

A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.

Neuromorphic device

A compressed-truncated singular value decomposition (C-TSVD) based crossbar array apparatus is provided. The C-TSVD based crossbar array apparatus may include an original crossbar array in an m×n matrix having row input lines and column output lines and including cells of a resistance memory device, or two partial crossbar arrays obtained by decomposing the original crossbar array based on C-TSVD, an analog to digital converter (ADC) that converts output values of column output lines of sub-arrays obtained through array partitioning, an adder that sums up results of the ADC to correspond to the column output lines, and a controller that controls application of the original crossbar array or the two partial crossbar arrays. Input values are input to the row input lines, a weight is multiplied by the input values and accumulated results are output as output values of the column output lines.

Crossbar array apparatuses based on compressed-truncated singular value decomposition (C-TSVD) and analog multiply-accumulate (MAC) operation methods using the same

A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

Method and apparatus with data processing

An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

Electronic system including FPGA and operation method thereof

A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.

Neuromorphic computing device and method of designing the same

An analog-to-digital converter is connected to a crossbar array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and processing circuitry. The voltage generator includes at least one resistive memory element including a same resistive material as the resistive element included in the crossbar array, and is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element and to divide the first voltage to generate at least one divided voltage. The processing circuitry is configured to compare a signal voltage generated from the crossbar array with the at least one divided voltage to generate at least one comparison signal and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

Analog-to-digital converter and neuromorphic computing device including the same

A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.

Ternary content addressable memory and operating method thereof

A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.

Synapse element increasing a dynamic range of an output while suppressing and/or decreasing power consumption, and a neuromorphic processor including the synapse element

A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

Semiconductor memory device for supporting operation of neural network and operating method of semiconductor memory device

A memory device includes a selection structure disposed on a common conductive region and including an array of spaced-apart vertical semiconductor pillars electrically coupled to the common conductive region, first horizontal selection lines extending in parallel above the common conductive region and including sidewall surfaces that face sidewalls of the vertical semiconductor pillars, second horizontal selection lines extending in parallel above and transverse to the first horizontal selection lines and including sidewall surfaces that face sidewall surfaces of the vertical semiconductor pillars and at least one dielectric pattern interposed between the first horizontal selection lines and the vertical semiconductor pillars and between the second horizontal selection lines and the vertical semiconductor pillars. The memory device further includes a memory cell array disposed on the selection structure and comprising memory cells electrically coupled to the vertical semiconductor pillars.

Growing community of inventors

Hwaseong-si, South Korea

Youngnam Hwang