Texas Instruments Corporation

Youngmin Kim

Amitava Chatterjee

Mahalingam Nandakumar

Seetharaman Sridhar

Shawn T Walsh

Mark Stephen Rodder

Zhiqiang (Jeff) Wu

Andrew Marshall

David Barry Scott

Craig Thomas Salling

Shaoping Tang

Song Zhao

Douglas E Mercer

Jaideep Mavoori

A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack () is formed over the silicon substrate (). Ion implantation is performed of a first species and a second species to produce the doping profiles () in the input-output transistors.

Tunable sidewall spacer process for CMOS integrated circuits

Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness

A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

High performance PNP bipolar device fully compatible with CMOS process

A method of forming a semiconductor circuit ( ). The method forms a first transistor (NT ) using various steps, such as by forming a first source/drain region ( ) as a first doped region in a fixed relationship to a semiconductor substrate ( ) and forming a second source/drain region ( ) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate ( ) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST ) using various steps, such as by forming a third source/drain region ( ) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region ( ) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate ( ) in a fixed relationship to the third source/drain region and the fourth drain region. Also in the preferred embodiment method, the steps of forming the first gate and the second gate comprising forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration.

Memory cell with transistors having relatively high threshold voltages in response to selective gate doping

An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. In the first embodiment, the space includes a dummy gate; in the second embodiment, an isolation region; in the third embodiment, the space a protected, stable surface.

Method to increase substrate potential in MOS transistors used in ESD protection circuits

An integrated semiconductor system is provided that is formed on a substrate . A dual implant mask is used to change the characteristics of semiconductor devices formed in regions of the substrate having different characteristics. Transistors and can be formed on the same substrate and have different electrical characteristics.

Transistors having selectively doped channel regions

A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.

Process of increasing screen dielectric thickness

An implant at HVGX pattern (step ) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.

Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask

A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region ( ) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer ( ) and gate layer ( ) are formed above the third well ( ) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Buried channel PMOS transistor in dual gate CMOS with reduced masking steps

A method of forming a poly-silicide gate electrode (102). The polysilicon deposition is broken into two steps. After the first polysilicon layer (102a) is formed, a very thin oxide (102b) is formed thereover. Polysilicon deposition then continues to form a second polysilicon layer (102c). The oxide layer (102b) inhibits grain growth resulting in a smaller grain size for the second polysilicon layer (102c). Prior to silicide formation, a pre-amorphization implant is performed to amorphize the second polysilicon layer (102c) and possibly some of the first polysilicon layer (102a) as well. Titanium is deposited and reacted with the polysilicon layers to form a silicide. The silicide process consumes the interface between polysilicon layers (102a & 102c) and possibly a portion of the first polysilicon layer (102a). The resulting silicide layer has a more uniform sheet resistance.

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Allen, TX, United States of America

Youngmin Kim