Samsung Electronics Co., Ltd.

Youngmin Choi

Hyunwook Lim

Jaeyoul Lee

Yong-Yun Park

Kyongho Kim

Jinho Kim

Kyungho Ryu

Kilhoon Lee

Kyungae Kim

Hyungwoo Lee

Minjoon Jung

Kwi Sung Yoo

Dong-hoon Baek

Eun-young Jin

Dohaeng Kim

Seunghwan Baek

Hyejoon Seok

Jong-Hee Na

Sangoh Yoo

Seungeun Chung

MyeongJun Chae

KeunHo Ryu

Byungkoan Kim

Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes 'M' consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

Electronic device and operating method of a decoder

Encoder generating data packet, operation method thereof, and operation method of electronic device including encoder

A clothes dryer is disclosed. The clothes dryer includes a rotatably disposed drum, a heat pump system including a compressor configured to compress a refrigerant and a condenser configured to condense the refrigerant, a heater configured to heat air supplied to the interior of the drum, a first temperature sensor configured to detect a temperature of air passing through the interior of the drum, a second temperature sensor configured to detect a temperature of the compressor, and a processor configured to control an operation of the compressor on the basis of the temperature of the air passing through the interior of the drum detected by the first temperature sensor and control an operation of the heater on the basis of the temperature of the compressor detected by the second temperature sensor.

Clothes dryer and control method thereof

An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.

Display device and interface operation thereof

A display driving device is disclosed which includes a source driver that supplies voltages to source lines connected to pixels, detects a slew time of the voltages of the source lines, and outputs the slew time, and a timing controller that receives the slew time from the source driver and updates a way for the source driver to control the voltages depending on the slew time.

Display driving device including source driver and timing controller and operating method for controlling source line slew times

An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel. The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.

A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

Clock and data recovery circuit detecting unlock of output of phase locked loop

Growing community of inventors

Yongin-si, South Korea

Youngmin Choi