Hyundai Motor Company

Kia Corporation

Kia Motors Corporation

Korea Institute of Science and Technology

Hyundai Autron Company Ltd.

Youngkyun Jung

Dae Hwan Chun

Jong Seok Lee

Junghee Park

Kyoung-Kook Hong

NackYong Joo

Jungyeop Hong

Jongseok Lee

Hyun Woo Noh

JongSeok Lee

Su Bin Kang

Nack Yong Joo

Jae Woo Choi

Sun Myung Choi

Youngjoon Kim

Hyuk Woo

Ung Su Choi

Kyung-Won Jung

Nackyong Joo

Taeyeop Kim

A method for manufacturing a semiconductor device includes forming an N-type layer on the first surface of the N+ type substrate, etching the N-type layer to form a trench, forming a sacrificial layer on an inner bottom surface of the trench, forming a first mask on an inner side of the trench, removing the sacrificial layer, and forming a P type shield region by implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer.

Method for manufacturing semiconductor device and semiconductor device manufactured thereby

The present disclosure relates to a self-regenerable fibrous adsorbent for heavy metal adsorption, which is capable of adsorbing heavy metal ions in water, growing them into crystals and desorbing the grown heavy metal crystals on its own, and a method for preparing the same. The self-regenerable fibrous adsorbent for heavy metal adsorption according to the present disclosure is a fibrous polymer consisting of PAN and PMMA, wherein amine functional groups are immobilized on the surface of the PAN and hydroxyl groups (—OH) are immobilized on the surface of the PMMA.

Self-regenerable fibrous adsorbent for heavy metal adsorption

Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

Semiconductor device and three-phase inverter comprising the same

A semiconductor device includes an N+ type substrate, an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N− type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (GaO) and the other includes silicon (Si).

Semiconductor module and method for manufacturing the same

A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (GaO) and the other includes silicon (Si).

Provided is a method of fabricating capsules. The method includes: forming droplets of a dispersed phase solution including a phase transition material, a carbon nanomaterial, and a first monomer by allowing the dispersed phase solution to pass through nozzle units provided at a porous membrane in a reaction tank including the porous membrane; migrating the droplets into a mobile phase material including a second monomer; and forming polymer shells at interfaces between the droplets and the mobile phase material by polymerization between the first monomer and the second monomer.

Method and apparatus for fabricating capsule

A Schottky barrier diode includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n&#x2212; type layer and separated from each other; an anode disposed on the n&#x2212; type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate. The p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n&#x2212; type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

Schottky barrier diode and method of manufacturing the same

A semiconductor device includes an n+ type silicon carbide substrate, an n&#x2212; type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.

Semiconductor device and method for manufacturing same

A manufacturing method of a semiconductor device is provided. The method includes sequentially forming an n&#x2212; type of layer, a p type of region, and an n+ type of region on a first surface of a substrate, forming a preliminary trench in the n&#x2212; type of layer by a first etching process and forming a preliminary gate insulating layer by a first thermal oxidation process. The method includes etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by a second etching process and forming a gate insulating layer in the trench by a second thermal oxidation process. The gate insulating layer includes a first and second portion. The preliminary first portion is thicker than the preliminary second portion and the first portion. The first portion thickness is equal to the thickness of the second portion.

Manufacturing method of semiconductor device to uniformly form thickness of gate insulating layer

A semiconductor device may include an n&#x2212; type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n&#x2212; type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n&#x2212; type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.

Semiconductor device and method manufacturing the same

A semiconductor device is provided. The device includes an n&#x2212; type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n&#x2212; type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n&#x2212; type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n&#x2212; type layer disposed therein.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n&#x2212; type layer; a p type region disposed on both side surfaces of the first trench; an n+ type region disposed on both side surfaces of the first trench and disposed on the n&#x2212; type layer and the p type region; a gate insulating layer disposed inside the first trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ region; and a drain electrode disposed on the second surface of the n+ type silicon carbide substrate, wherein a first channel as an accumulation layer channel and a second channel as an inversion layer channel are disposed in both side surfaces of the first trench, and the first channel and the second channel are disposed to be adjacent in a horizontal direction for the first surface of the n+ type silicon carbide substrate.

Semiconductor device comprising accumulation layer channel and inversion layer channel

A semiconductor device includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n&#x2212; type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n&#x2212; type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

Growing community of inventors

Seoul, South Korea

Youngkyun Jung