Winbond Electronics Corporation

Youngjoo Choi

Chan-Seok Park

Young-Tae Kim

Myung-Chan Choi

A latency control circuit and method are provided. The latency control circuit includes a DLL circuit, a latency counter circuit, a synchronization circuit, and a delay line circuit. The DLL circuit enters an inactive state after locking the delay time and provides an active signal at a disable state, delay locking information and loop delay information during the inactive state. The synchronization circuit stops providing a first clock signal according to the active signal at the disable state and then synchronously outputs an operation enabling signal and a second clock signal in response to an enablement of the operation signal. The delay line circuit receives the delay locking information, the operation enabling signal, and the second clock signal and outputs an operation delay signal and an output clock signal after the delay time.

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San Jose, CA, United States of America

Youngjoo Choi