Samsung Electronics Co., Ltd.

Youngjin Chung

Jaechul Park

Hong-mook Choi

Jaehyun Park

Hanseok Kim

Jonghoon Shin

Jongshin Shin

Heonsoo Lee

Wonsuk Jang

Hobin Song

Sangyun Hwang

Ingoo Heo

Seungsik Eom

An electronic device includes an analog front end (AFE) circuit including plural modules, and a processor that provides a user interface for a firmware update, determines a target module, of which offset calibration is to be performed, among the plural modules, based on a user input to the user interface, determines a position within in the AFE circuit to which a common mode voltage is to be applied to perform the offset calibration of the target module, and determines an offset calibration sequence including the target module and the position.

Electronic device and offset calibration method

An integrated circuit may include a receiver configured to receive a first data signal based on an m(where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

Integrated circuit and operation method thereof

An encryption device includes a counter, an encryption/decryption unit, and a timer. The counter is configured to generate a first timestamp for a first time. The encryption/decryption unit is configured to concatenate security data and the first timestamp, encrypt the concatenated data into encryption data, transmit the encryption data to a memory device, and decrypt read data transmitted from the memory device into decryption data. The timer is configured to inform the counter and the encryption/decryption unit that a time elapses from the first time to a second time such that the counter generates a second timestamp for the second time and the encryption/decryption unit decrypts the read data into the decryption data. Checking logic implemented by the encryption device is configured to check whether a decryption timestamp of the decryption data is identical to the first timestamp.

Encryption device for encrypting data and timestamp, system on chip including the same, and electronic device

A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.

Computing system having an on-the-fly encryptor and an operating method thereof

Growing community of inventors

Seongnam-si, South Korea

Youngjin Chung