Samsung Electronics Co., Ltd.

Youngji Noh

Sanghun Chun

Junghwan Park

Jeehoon Han

Shinhwan Kang

Donghwan Kim

Kwangyoung Jung

Jung-Hwan Park

A three-dimensional semiconductor device includes a plate common source line, first and second word lines spaced apart from each other to at least partially define a vertical space therebetween, a channel pattern in the vertical space, a ferroelectric layer including a first portion between the channel pattern and the first word line, a second portion between the channel pattern and the second word line, and a third portion contacting the plate common source line, a bit line in the vertical space to contact the channel pattern and having a first width in a first horizontal direction, and a source line spaced apart from the bit line in the vertical space to contact the channel pattern, having a second width greater than the first width in the first horizontal direction, and having a source line contact portion inside the plate common source line.

Three-dimensional semiconductor device including ferroelectric transistor

Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.

Three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same

A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

Semiconductor devices comprising crack preventing layers and data storage systems including the same

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Suwon-si, South Korea

Youngji Noh