Samsung Electronics Co., Ltd.

Youngjae Son

Byung-Ho Kang

Yongjin Yoon

Taemin Earmme

Seungchul Han

Guesuk Lee

Hyeongyun Lee

Disclosed are chuck assemblies, semiconductor device fabricating apparatuses, and methods of fabricating semiconductor devices. The chuck assembly comprises a chuck base including lower and upper bases, a ceramic plate on the upper base, an edge ring that surrounds the ceramic plate, a ground ring that surrounds an outer sidewall of the edge ring on an edge portion of the lower base, a coupling ring between the ground ring and the upper base and between the edge ring and the edge portion of the lower base, an upper heat sink between the coupling ring and the edge ring, and a sidewall heat sink between the coupling ring and the ground ring and between the coupling ring and the upper base.

Chuck assembly, semiconductor device fabricating apparatus including the same, and method of fabricating semiconductor device

Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit.

Random access memory devices having word line drivers therein that support variable-frequency clock signals

Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit. The word line driver circuit is further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit.

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Hwaseong-si, South Korea

Youngjae Son