Skhynix Inc.

Seoul National University

Pohang University of Science and Technology Foundation

Youngjae Jin

Jin Wook Kim

Jae-Joon Kim

Joonwoo Kim

Jae In Lee

Sungjoo Yoo

Youngsuk Moon

Junki Park

Youngook Song

Seunghwan Cho

Euiseok Kim

A method for pruning a neural network includes initializing a plurality of threshold values respectively corresponding to a plurality of layers included in the neural network; selecting one of the plurality of layers; adjusting the threshold value of the selected layer; and adjusting a plurality of weights respectively corresponding to a plurality of synapses included in the neural network.

Method and device for pruning a neural network

A method for formatting a weight matrix including a plurality of sub matrices each being multiplied with an input vector may include sequentially adding weight information included in respective first columns of the plurality of sub matrices to formatted data; and sequentially adding weight information included in respective second columns of the plurality of sub matrices to the formatted data after the weight information from the first columns of the plurality of sub matrices. The weight information may be non-zero weight information.

Method of formatting a weight matrix, an accelerator using the formatted weight matrix, and a system including the accelerator

A memory device may include a memory medium and a memory controller. The memory medium may be configured to perform a self-refresh operation and an auto-refresh operation in response to a self-refresh signal and an auto-refresh control signal, respectively. The memory controller may be configured to control the auto-refresh operation by transmitting the auto-refresh control signal to the memory medium. The memory medium includes a self-refresh controller. The self-refresh controller may be configured to control the self-refresh operation based on a self-refresh cycle varying according to an internal temperature of the memory medium and transmit the self-refresh signal to the memory controller. The memory controller may be configured to generate the auto-refresh control signal based on an auto-refresh cycle. The auto-refresh control signal may be determined by the self-refresh signal transmitted from the memory medium.

Memory devices and methods of controlling an auto-refresh operation of the memory devices

A semiconductor memory device includes a cell circuit including a plurality of cell dies arranged in a cell die stack. The semiconductor device also includes a control circuit configured to control the cell circuit, wherein the control circuit includes an address decoder and an address conversion circuit. The address decoder is configured to decode an address signal provided by a host and to output address information including a first address which identifies a first cell die, of the plurality of cell dies, requested by the host. The address conversion circuit is configured to convert the first address to a second address using the address information and to provide the second address to the cell circuit, wherein the second address is used to identify a second cell die of the plurality of cell dies different from the first cell die.

Semiconductor memory device for controlling an address for temperature management

A memory device includes a memory medium and a memory controller. The memory medium has a memory cell array and may be configured to generate a self-refresh signal, which varies based on an internal temperature of the memory medium, to control a self-refresh operation performed on the memory cell array. The memory controller may be configured to calculate an auto refresh cycle of an auto refresh control signal for controlling an auto-refresh operation of the memory medium based on the self-refresh signal.

An electronic device includes an area control signal generation circuit and an area column control signal generation circuit. The area control signal generation circuit generates an area control signal in response to an operation control signal and an internal information signal. The area control signal includes information on whether each of a plurality of cell areas performs an error correction operation. The area column control signal generation circuit delays a column pulse signal for a delay period, which is determined according to the area control signal, to generate an area column control signal that controls a column operation of the plurality of cell areas.

Electronic devices

In an embodiment a semiconductor device may include a weakness detector configured to manage error occurrence information by dividing the memory device into a plurality of areas, to control a first refresh period for a first refresh request at each of the plurality of areas based on the error occurrence information and to generate a second refresh request for a second refresh address included in each of the plurality of areas based on the error occurrence information, and a refresh controller configured to generate a first refresh command according to the first refresh period and output the first refresh command to the memory device and to output a second refresh command and the second refresh address to the memory device according to the second refresh request and the second refresh address.

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Seoul, South Korea

Youngjae Jin