Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Samsung Electro-mechanics Co., Ltd.

Younghwan Park

Jaejoon Oh

Sunkyu Hwang

Soogine Chong

Joonyong Kim

Injun Hwang

Dongchul Shin

Byeonghyeon Ju

Kiyeol Park

Woochul Jeon

Daegyu Kim

Jaehyun Lim

Joonho Pyo

Kyounghoon Kim

Boram Kim

Shinwoo Han

Hansu Cho

Sukjin Kim

Junhee Choi

Seungwon Lee

Seungjoon Lee

Taehee Lee

Junhyuk Park

Hyunjung Kim

Inho Choi

Jiwon Lee

Joohun Han

Sangheon Yoon

Nakhyun Kim

Jongseob Kim

Sangwoo Woo

Junghun Park

Yongjin Choi

Sang-Yeop Baeck

Eunsung Lee

Kwangjin Lee

Inhak Lee

Joosung Kim

Jungbin Yun

Seunghun Kim

Moonkee Chung

Moosup Lim

Jaechul Lee

Hyuntaek Choi

Jaesung Choi

Haewon Lee

Kang-sun Lee

Minchul Yu

Jeongjin Cho

Keshava Prasad Nagaraja

Dongha Lee

Dongkwan Suh

Kiyoung Kang

Minhan Kim

Sangjoo Lee

Dongjoo Yang

Minkyung Jung

Keshava Prasadnagaraja

Hyoseon Jang

Kyunghwa Park

A semiconductor device package includes a lead frame, a semiconductor device including a first face connected to the lead frame, a second face that faces the first face, a gate pad, a drain pad, and a source pad, the gate pad exposed on the second face of the semiconductor, the drain pad exposed on the second face of the second face, and the source pad exposed on the second face, a gate clip connected to the gate pad, a drain clip connected to the drain pad, a source clip connected to the source pad, the source clip connected to the lead frame, and a molding that seals the lead frame, the semiconductor device, the source clip, the drain clip, and the gate clip.

Semiconductor device package

Provided are nanorod light emitting diodes (LEDs), display apparatuses, and manufacturing methods thereof. The nanorod LED includes a first-type semiconductor layer including a body and a pyramidal structure continuously provided from the body, a nitride light emitting layer provided on the pyramidal structure, and a second-type semiconductor layer provided in the nitride light emitting layer.

Nanorod LED, display apparatus including the same, and method of manufacturing the nanorod LED

A high electron mobility transistor includes a channel layer; a barrier layer on the channel layer and having an energy bandgap greater than an energy bandgap of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending above the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer may extend toward the gate structure.

High electron mobility transistor

Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

Semiconductor device package and method of fabricating the same

A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

Semiconductor IC device including passivation layer for inactivating a dopant in a p-type semiconductor layer and method of manufacturing the same

A nitride semiconductor device having a field effect gate is disclosed. The disclosed nitride semiconductor device includes a high-resistance material layer including a Group III-V compound semiconductor, a first channel control layer on the high-resistance material layer and including a Group III-V compound semiconductor of a first conductivity type, a channel layer on the channel layer control layer and including a nitride semiconductor of a second conductivity type opposite to the first conductivity type, and a gate electrode having a contact of an ohmic contact type with the first channel control layer.

Nitride semiconductor device with field effect gate

Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

High electron mobility transistor and method of manufacturing the same

A fingerprint sensor package may include a film substrate, an interconnection substrate on the film substrate, a semiconductor chip on the interconnection substrate, a conductive structure on the interconnection substrate and laterally isolated from direct contact with the semiconductor chip, and an interposer substrate on the semiconductor chip and the conductive structure. The conductive structure may include first and second conductive structures, which are electrically separated from each other. The interposer substrate may include a first sensing pattern electrically connected to the first conductive structure and a second sensing pattern on a top surface of the first sensing pattern and electrically connected to the second conductive structure. The second sensing pattern may be vertically isolated from direct contact with from the first sensing pattern. The second sensing pattern may have a longitudinal axis parallel to a direction crossing a longitudinal axis of the first sensing pattern, in a plan view.

Fingerprint sensor package and sensor package

A fingerprint sensor package includes a first substrate including a core insulating layer; a first bonding pad on the core insulating layer; and an external connection pad between an edge of the second surface of the core insulating layer and the first bonding pad, a second substrate on the core insulating layer, the second substrate including: a plurality of first sensing patterns spaced apart in a first direction and extending in a second direction intersecting with the first direction; a plurality of second sensing patterns spaced apart from each other in the second direction and extending in the first direction; and a second bonding pad, a conductive wire connecting the first bonding pad to the second bonding pad; a controller chip on the second substrate; and a molding layer covering the second substrate and the first bonding pad and spaced apart from the external connection pad.

Fingerprint sensor package and smart card including the same

Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

Field effect transistor including gradually varying composition channel

Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

Static random access memory device

A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

Semiconductor device and method of fabricating the same

A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.

A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

Semiconductor thin film structures and electronic devices including the same

A fingerprint sensor package includes a package substrate including an upper surface in which a sensing region and a peripheral region surrounding the sensing region are defined, and a lower surface facing the upper surface; a plurality of first sensing patterns located are arranged in the sensing region, are apart from each other in a first direction, and extend in a second direction crossing the first direction; a plurality of second sensing patterns that are arranged in the sensing region, are apart from each other in the second direction, and extend in the first direction; a coating member covering the sensing region; an upper ground pattern in the peripheral region and apart from the coating member to surround the coating member in the first and second directions; and a controller chip on the lower surface of the package substrate; and a plurality of capacitors.

Fingerprint sensor package and smartcard including the same

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Seoul, South Korea

Younghwan Park