Samsung Electronics Co., Ltd.

Younghun Seo

Dongil Lee

Hoseok Lee

Sun Young Kim

Sang-yun Kim

Sangyun Kim

Myungkyu Lee

Sunghye Cho

Sunyoung Kim

Kyungryun Kim

Seungjun Shin

Hye Jung Kwon

Bokyeon Won

Hyejung Kwon

Juwon Lim

Kangsub Jeong

DongHyeok Cho

Jaekoo Park

Yeongwoo Kang

Duckyoung Seo

Soobong Chang

A method of operating a bit line sense amplifier may include performing a normal precharge operation by charging a bit line, a complementary bit line, a sensing bit line, and a complementary sensing bit line to a precharge voltage, and then performing a first offset compensation operation by connecting the bit line to the sensing bit line, connecting the complementary bit line to the complementary sensing bit line, applying a first internal voltage greater than the precharge voltage to a P-type sense amplifier, and applying a second internal voltage less than the precharge voltage to an N-type sense amplifier. A second offset compensation operation is performed by applying the precharge voltage to the P-type sense amplifier concurrently with applying the second internal voltage to the N-type sense amplifier. A bit line offset detection operation is performed by separating the bit line from the sensing bit line, separating the complementary bit line from the complementary sensing bit line, connecting the sensing bit line to the complementary sensing bit line, and applying the precharge voltage to the N-type sense amplifier.

Memory devices having sense amplifiers therein that support offset compensation and methods of operating same

Disclosed is a sense amplifier which includes a sense amplification circuit and a sensitivity control circuit. The sense amplification circuit includes first and second MOS transistors. The first MOS transistor is connected with a first bit line and a target memory cell. The second MOS transistor is connected with a second bit line and a non-target memory cell. The sense amplification circuit pre-charges the first and second bit lines with a first driving voltage, compensates for an offset, and senses the target data based on a change in a voltage level of the first bit line, after charge sharing between the target memory cell and the first bit line. The sensitivity control circuit adjusts the sensing sensitivity for the target data indicating a first logical value by increasing a magnitude of a current flowing through the first MOS transistor while the sense amplification circuit senses the target data.

Sense amplifier, operating method thereof, and volatile memory device including the same

A semiconductor memory device includes: a memory cell array located in a first layer and including a word line, a cell bit line, and a memory cell located in a region where the word line and the cell bit line are crossed; and a bit line sense amplifier located in a second layer, different from the first layer. The bit line sense amplifier is connected to a bit line that is connected to the cell bit line and to a complementary bit line corresponding to the bit line. The bit line sense amplifier detects data stored in the at least one memory cell. Each of the at least one cell bit line is segmented into two or more portions, and the two or more portions are respectively connected to the bit line and the complementary bit line connected to the bit line sense amplifier.

Semiconductor memory device having segmented cell bit line

A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

Memory core circuits having cell-on-periphery structures and memory devices including the same

A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.

Semiconductor memory device capable of adaptively controlling bias and method of operating the same

Disclosed is a memory device which includes a first memory cell that is electrically connected with a first word line and a first bit line, a first bit line sense amplifier circuit that is electrically connected with the first bit line, a first local sense amplifier circuit that is electrically connected with the first bit line sense amplifier circuit through a first local input/output line, a first local driver that is electrically connected with the first local sense amplifier circuit through a first pre-global input/output line, and a sense amplifier and write driver that is electrically connected with the first local driver through a global input/output line, and the first local driver selectively electrical-disconnects the first pre-global input/output line from the global input/output line, based on an operation for the first memory cell.

Memory device

A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

Bit line sense amplifier and semiconductor memory device having the same

A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

Semiconductor memory devices including sense amplifier adjusted based on error information

A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

Volatile memory device and data sensing method thereof

Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.

Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I/O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding a command received from a memory controller. The ECC engine is configured to a first parity data based on a first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data in the parity region based on a receiving timing of a second command successive to the first command and a reference time interval.

Semiconductor memory devices, and methods of operating semiconductor memory devices

A semiconductor memory device includes a memory cell that stores multi-bit data, and a bit line sense amplifier that is connected to a bit line of the memory cell and a complementary bit line corresponding to the memory cell in an open bit line structure. The bit line sense amplifier includes a first latch that sequentially senses a first bit and a second bit of the stored multi-bit data and transmits the sensed first bit to a second latch, and a second latch that senses the transmitted bit from the first latch.

Bit line sense amplifier, semiconductor memory device and multi bit data sensing method thereof

A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.

Voltage trimming circuit and integrated circuit including the voltage trimming circuit

A sense amplifier includes a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. The sense amplifier further includes a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal.

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Hwaseong-si, South Korea

Younghun Seo