Samsung Electronics Co., Ltd.

Younghoon Son

Junghwan Choi

Youngdon Choi

Jindo Byun

Hyungmin Jin

Hyunyoon Cho

Jaewoo Park

Junyoung Park

Sucheol Lee

Youngdo Um

Sukhee Cho

Kwangseob Shin

Sangwoo Kim

Mingyu Lee

Joohwan Kim

Joungyeal Kim

Seongheon Yu

Hyeokjun Choi

Chulung Kim

A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

Memory device supporting a high-efficient input/output interface and a memory system including the memory device

In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same

An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.

Apparatus, memory device, and method reducing clock training time

A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.

Translation device, test system including the same, and memory system including the translation device

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

Memory device, method of calibrating signal level thereof, and memory system having the same

A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

Probe device, test device, and test method for semiconductor device

A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.

Transmitters for generating multi-level signals and memory system including the same

A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.

Memory device, controller controlling the same, memory system including the same, and operating method thereof

A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

Memory package and storage device including the same

A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Method of generating a multi-level signal using a selective level change, a method of transmitting data using the same, and a transmitter and memory system performing the same

A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M&#x2212;1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M&#x2212;1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M&#x2212;1) reference voltages, At least two sense amplifiers of the (M&#x2212;1) sense amplifiers have different sensing characteristics.

Multi-level signal receivers and memory systems including the same

A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

Memory device for receiving one clock signal as a multi-level signal and restoring original data encoded into the clock signal and method of operating the same

A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

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Yongin-si, South Korea

Younghoon Son