Dsp Group Limited

Texas Instruments Corporation

Younggyun Kim

Jaekyun Moon

Bhavesh G Bhakta

Barrett J Brickner

Michael E Butenhoff

Paul C Edwards

David Richard Gruetter

Ming-Tak Leung

Taehyun Jeon

Leo Ki-Chun Fu

Farshid R Rad

Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Digital phase locked loop

An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality

Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter, a feedback intersymbol interference (ISI) canceller, a transform unit, a phase rotation estimator and corrector, a pattern-dependent bias canceller, and a maximum picker for symbol decisions. The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.

CCK demodulation via symbol decision feedback equalizer

Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

Digital front-end for wireless communication system

A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.

Joint equalization, soft-demapping and phase error correction in wireless system with receive diversity

A phase lock loop to control phase error including a first phase error detector to detect the phase error in a first mode, a first loop filter to filter a first phase error by using a first factor, a second phase error detector to detect a second phase error in a second mode, a second loop filter to filter a second phase error by using a second factor, and a circuit to select either the first phase error or the second phase error in accordance with the first or second mode.

Implementation method of digital phase-locked loop

A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

Decision error compensation technique for decision-directed timing recovery loop

A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr; &equals;(z &minus;y ) &minus;&agr; , wherein &agr; is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr; is a branch metric at time k for an i Viterbi branch, k is a time period, z is a received value at time k, &lgr; is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an i branch, a , a , a , a are received state values at respective time periods k, k&minus;1, k&minus;2, and k&minus;3, and y is an ideal sample associated with an i branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first ( ) and second ( ) possible decode values. The space has a boundary ( ) substantially equidistant from the first ( ) and second ( ) possible decode values and separating the first and second possible decode values. If the received value is within a first portion of the space closest to the first decode value, the received value is decoded as the first decode value. If the received value is within a second portion of the space closest to the second decode value, it is decoded as the second decode value. A value (&agr;) that estimates an amount of jitter noise in a channel ( ) through which the received value has passed is produced. The boundary ( ) is then moved an additive amount (1&agr;, 2&agr;, 3&agr;) determined by the value that estimates an amount of jitter noise, wherein the boundary is moved ( ) to enlarge whichever of the first and second spaces that contains a larger amount of jitter noise.

Modified viterbi detector for jitter noise dominant channels

A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.

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Irvine, CA, United States of America

Younggyun Kim