Samsung Electronics Co., Ltd.

Younggwan Ko

Myungsam Kang

Bongju Cho

Gun Goo Lee

Youngchan Ko

Yongkoon Lee

Moonil Kim

Jaekul Lee

Taesung Jeong

Jaeean Lee

Jungsoo Byun

Changbae Lee

Yongjin Park

Hanul Lee

A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.

Interposer and semiconductor package including the same

A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate.

Semiconductor package

A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

Package module

A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

Fan-out semiconductor package

A semiconductor package includes: a connection structure including one or more redistribution layers; a core structure disposed on a surface of the connection structure; a semiconductor chip disposed on the surface and including connection pads electrically connected to the redistribution layers of the connection structure; a first encapsulant disposed on the surface and covering at least a portion of each of the core structure and the semiconductor chip; an antenna substrate disposed on the first encapsulant and including one or more wiring layers, at least a portion of the wiring layers including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the core structure, the first encapsulant, and the antenna substrate.

A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.

A fan-out semiconductor package includes a frame including a plurality of wiring layers electrically connected to each other and having a recess portion having a bottom surface on which a stopper layer is disposed, a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer, an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion, and a connection structure disposed on the frame and the active surface and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad. A thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers.

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Suwon-si, South Korea

Younggwan Ko