Samsung Electronics Co., Ltd.

Younggul Song

Junyeong Seok

Eun Chu Oh

Byungchul Jang

Joonsung Lim

Eunchu Oh

Wijik Lee

MinHo Kim

A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

Non-volatile memory device and method of manufacturing the same

A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.

Memory device, memory system, and method of operating the memory system

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

Storage devices and methods of operating storage devices

A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.

In a method of reprogramming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, first page data programmed in a first page is read from among a plurality of page data programmed in the plurality of pages. The plurality of page data have a threshold voltage distribution including a plurality of states. An error correction code (ECC) decoding is performed on the first page data. A reprogram operation is selectively performed on target bits in which an error occurs among a plurality of bits included in the first page data based on a result of performing the ECC decoding on the first page data and a reprogram voltage. The target bits correspond to a first state among the plurality of states. A voltage level of the reprogram voltage is adaptively changed.

Method of reprogramming data in nonvolatile memory device, method of programming data in nonvolatile memory device, nonvolatile memory device performing the same, and method of operating nonvolatile memory device using the same

A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

Storage device using wafer-to-wafer bonding and method of manufacturing the same

A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

Nonvolatile memory devices for reducing degradation due to difference of threshold voltage distributions between outer cells and inner cells

A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

Method of operating nonvolatile memory device, nonvolatile memory device and memory controller performing the same

A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.

Memory system for performing recovery operation, memory device, and method of operating the same

A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Growing community of inventors

HWASEONG-SI, South Korea

Younggul Song