Samsung Electronics Co., Ltd.

Younggeon Yoo

Junjin Kong

Jeongho Lee

Wonseb Jeong

Hong Rak Son

Hyeokjun Choe

Chanho Yoon

Younho Jeon

Ipoom Jeong

Changkyu Seol

Eun Chu Oh

Jaeho Shin

Yang Seok Ki

Sangoak Woo

Beomkyu Shin

Jungmin Seo

Myungjune Jung

Hyodeok Shin

Youngjin Cho

Kijun Lee

Soo-Young Ji

Hee Hyun Nam

Hyeonwu Kim

Kwanghoon Kim

Heehyun Nam

Sang-Hwa Jin

JeongHo Lee

Junghyun Hong

Hyunseuk Yoo

Hyeongseok Song

A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Storage device, operation method of storage device, and storage system using the same

A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

Storage system utilizing transaction layer packet contained steering information

The present disclosure provides methods and apparatuses for data loss prevention of a storage device. In some embodiments, the data loss preventing method includes receiving, from a host system, a query plan corresponding to necessary data to be stored in a volatile memory. The data loss preventing method further includes generating, based on the query plan, a data priority list corresponding to the necessary data. The data loss preventing method further includes selecting, based on the data priority list, at least one portion of the volatile memory, when a main power supplied by the host system drops to or below a power level threshold. The data loss preventing method further includes moving the necessary data to the at least one portion of the volatile memory.

Storage device preventing loss of data in situation of lacking power and operating method thereof

In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.

Method of allocating and protecting memory in computational storage device, computational storage device performing the same and method of operating storage system using the same

A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

System, device and method for accessing device-attached memory

A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

Storage system and method to perform workload associated with a host

A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.

System, device and method for indirect addressing

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

Storage device having a controller that communicates with each of two memories through separate interfaces

A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

Storage device supporting multi-tenancy and operating method thereof

A write method of a storage device including at least one nonvolatile memory device and a memory controller controlling the nonvolatile memory device includes dividing write data into a plurality of page data groups, each page data group including multiple bits of data; encoding the divided page data groups using different binary codes, respectively; mapping the encoded page data groups; programming, in first memory cells connected to one word line, programming states to which binary values of each of the mapped encoded page data groups are mapped, such that, the plurality of page data groups correspond respectively to a plurality of read voltage levels, and for each of the plurality of page data groups, the page data group can be read by performing a single read operation on the first memory cells using the read voltage level corresponding to the page data group.

Storage device and method of writing and reading the same

An operation method of a nonvolatile memory system in accordance with example embodiments of inventive concepts includes detecting an on-cell count of the memory cells using a sampling start voltage, comparing the detected on-cell count with a reference value, setting a plurality of sampling voltages based on the comparison result, performing a sampling operation with respect to the memory cells using the sampling voltages, and detecting an optimum read voltage for distinguishing any one program state among the program states based on a result of the sampling operation.

Operation method of nonvolatile memory system

Disclosed is a bit-state mapping method of a flash memory system which maps m-bit data (m being a natural number more than 2) onto one of 2states (voltage threshold distributions). The bit-state mapping method includes performing a subset partitioning operation during first to (m&#x2212;1)th levels under a condition that two adjacent states are processed as one state; and distinguishing between the adjacent states while processing an (m)th level.

Code modulation encoder and decoder, memory controller including them, and flash memory system

A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits.

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Seoul, South Korea

Younggeon Yoo