Himax Imaging, Inc.

Youngchul Sohn

Kwangoh Kim

Amit Mittra

Hack Soo Oh

Kihong Kim

Xufeng Bao

A CMOS image sensor includes: a substrate containing a potential well stack including: a first p-well, a first n-well disposed below the first p-well, a second p-well disposed below the first n-well, a second n-well disposed below the second p-well, and a third p-well disposed below the second n-well, wherein a first photodiode is formed at the junction between the first p-well and first n-well, a second photodiode is formed at the junction between the first n-well and second p-well, a third photodiode is formed at the junction between the second p-well and the second n-well, and a fourth photodiode is formed at the junction between the second n-well and the third p-well, and each photodiode is disposed at a different respective depth within the substrate; and a plurality of active pixel sensors for converting light received by the photodiodes into electrical charge.

CMOS RGB-IR sensor with quadruple-well stack structure

A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.

Phase-locked loop with a sampling circuit

An automatic exposure (AE) imaging system includes an image sensor that captures an analog image; an analog-to-digital converter (ADC) that converts the analog image into a digital image; a single-frame image processor that processes the digital image; an exposure quantizer that generates a discrete number representing a determined exposure time according to an output of the single-frame image processor; a multi-exposure controller, under control of a motion-detect signal, generating a plurality of different exposure times in sequence in each frame period in a motion detection mode, and outputting the determined exposure time in a streaming mode; and a pixel controller coupled to receive an output of the multi-exposure controller, according to which the image sensor is controlled.

Automatic exposure imaging system and method

An anti-eclipse circuit for use in an imager includes a differential amplifier and a feedback circuit. The differential amplifier is coupled to an output line for receiving an output signal associated with the voltage level of a floating diffusion region in a pixel of the imager and configured to detect when a reset signal received from the pixel drops below a predetermined level. The feedback circuit is configured to increase the reset signal when the output signal is lower than the clamp voltage, thereby keeping the reset signal at the constant level.

Anti-eclipse circuit and related imager

A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.

Digital double sampling circuit

An analog block implemented with a band-gap reference scheme for use in a device includes a mode control unit and a band-gap reference circuit. The mode control unit is configured to generate a mode selection signal associated with the operational mode of the device. The band-gap reference circuit includes a bias generator, an error amplifier, and a band-gap loop circuit. The bias generator is configured to provide a band-gap reference voltage in a first bias state when the device operates in a normal mode or in a second bias state when the device operates in a standby mode. The error amplifier is configured to generate an error voltage according to the bias voltage. The band-gap loop circuit is configured to provide a band-gap reference voltage according to the error voltage. First current flowing through the bias generator in the first bias state is larger than second current flowing through the bias generator in the second bias state.

Analog block implemented with band-gap reference scheme and related driving method

An image processing system for an image sensor includes an analog-to-digital conversion (ADC) unit that performs ADC on pixel signals, thereby generating digital pixel signals; a correlated double sampling (CDS) unit that performs CDS on the digital pixel signals; a black level estimation (BLE) unit that generates a negative offset voltage according to dark voltage obtained from CDS performed on estimating optical black pixels (OBPs) of a pixel array, the negative offset voltage being subtracted from the pixel signals before feeding the pixel signals to the ADC unit; and a black level compensation (BLC) unit that performs BLC on active pixels sensors (APSs) and the compensating OBPs of the pixel array.

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Tainan, Taiwan

Youngchul Sohn