Samsung Electronics Co., Ltd.

Youngchul Cho

Junghwan Choi

Youngdon Choi

Seungjin Park

Hojun Yoon

Mingyu Lee

Doobock Lee

Wonjoo Jung

Jaewoo Park

Baek Jin Lim

Seunghoon Lee

Dongsoo Lee

Changsik Yoo

Byeoungwook Kim

ChangSik Yoo

Jinha Hwang

Young Kil Choi

Baekjin Lim

Kwanghoon Son

A semiconductor device includes a first power node configured to supply a first power supply voltage, a pull-up circuit electrically connected between the first power node and an output node that is configured to output a signal, and a controller configured to output a pull-up control code to the pull-up circuit. The pull-up circuit includes a plurality of unit circuits electrically connected to each other in parallel between the first power node and the output node, and the plurality of unit circuits include a first unit circuit and a second unit circuit. The number of current paths provided by the first unit circuit between the first power node and the output node is different from the number of current paths provided by the second unit circuit between the first power node and the output node.

Semiconductor device

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

Memory device and operating method of a memory device

An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.

Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device

There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

Semiconductor device and method for preforming emphasis driving

An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.

Operational transconductance amplifier circuit including active inductor

A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

Quadrature error correction circuit and semiconductor memory device including the same

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Semiconductor memory device and memory system including the same

Clock signal delay path unit and semiconductor memory device including the same

An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

Injection locking oscillator circuit and operating method

A data compression method and a data decompression method are provided. The method includes pruning an original data including a plurality of weight parameters, identifying at least one first weight parameter of which at least one first value is not changed by the pruning, among multiple weight parameters included in the pruned original data, and obtaining a first index data including location information of the at least one first weight parameter of which the at least one first value is not changed, identifying at least one second weight parameter of which at least one second value is changed by the pruning, among the multiple weight parameters included in the pruned original data, and substituting the at least one second weight parameter of which the at least one second value is changed with a don't care parameter.

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Suwon-si, South Korea

Youngchul Cho