Samsung Electronics Co., Ltd.

Youngcheon Kwon

Jaeyoun Youn

Haesuk Lee

Jemin Ryu

Kyomin Sohn

Jihyun Choi

Sukhan Lee

Sanghyuk Kwon

Jaesan Kim

Reum Oh

Seongil O

Namsung Kim

Kijun Lee

Myungkyu Lee

Sunghye Cho

Sanguhn Cha

Yesin Ryu

Beomyong Kil

Hyunsung Shin

SeungHan Woo

A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

Memory device for supporting new command input scheme and method of operating the same

A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

Semiconductor device using different types of through-silicon-vias

A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

Memory device performing configurable mode setting and method of operating the same

A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same

A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

Memory devices including processing elements, and memory systems including memory devices

A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

Semiconductor memory device and system including the same

A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device

A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

Semiconductor memory devices and memory systems

High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.

Growing community of inventors

Hwaseong-si, South Korea

Youngcheon Kwon