Stats Chippac Pte. Ltd.

Chippac, Inc.

Youngcheol Kim

TaeKeun Lee

Marcos Karnezos

Flynn P Carson

Koo Hong Lee

Rajendra D Pendse

Hyeog Chan Kwon

Gwang Kim

Myung Kil Lee

Tae Sung Jeong

Yongmin Kim

Youngmin Kim

GuiChea Na

GwangJin Kim

Seng Guan Chow

Il Kwon Shim

Heap Hoe Kuan

Hun Teak Lee

Tae Keun Lee

DaeWook Yang

Kwang Soon Hwang

A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Semiconductor device and method of forming hybrid TIM layers

A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR&#x2212;2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Filp chip interconnection structure with bump on partial pad and method thereof

An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer.

Integrated circuit package system with mold gate

A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.

Integrated circuit packaging system with reinforced encapsulant having embedded interconnect and method of manufacture thereof

A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.

Thin package system with external terminals and method of manufacture thereof

An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

Inter-stacking module system

A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.

Stacked integrated circuit and package system and method for manufacturing thereof

A thin package system with external terminals and a leadframe is provided. An external bond finger defining template is provided and used to form external bond fingers on the leadframe. A die is provided and attached to the leadframe. At least portions of the die and the external bond fingers are encapsulated, and the leadframe is removed.

Thin package system with external terminals

A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.

Stacked integrated circuit and package system

A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package

Flip chip interconnection structure with bump on partial pad and method thereof

A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.

Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package

A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

Growing community of inventors

Youngin-si, South Korea

Youngcheol Kim