Samsung Electronics Co., Ltd.

Young-Wug Kim

Hee-Sung Kang

Chang-Bong Oh

Hyuk-Ju Ryu

Chang-bong Oh

Kyung-soo Kim

Hee-sung Kang

Dae-Lok Bae

Hyuk-ju Ryu

Mu-Kyoung Jung

Young-Jae Kwon

Chong-Mu Lee

Shigenobu Maeda

Kyung-Tae Lee

Jin-Won Jun

Tae-Soo Park

An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

Methods for fabricating reduced floating body effect static random access memory cells

In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate. As a result, a gate dielectric layer is formed to include a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the remaining first dielectric layer, and a thin portion formed of the third dielectric layer.

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

Semiconductor device and method of manufacturing the semiconductor device

Reduced floating body effect static random access memory cells and methods for fabricating the same

A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

Method of forming dual damascene interconnection using low-k dielectric

An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region. Because the SRAM is formed on the SOI substrate, the size of the resulting chip can be reduced. Also, because the channels of the first and second load PMOS transistors extend so that carriers move in the [110] silicon crystallization growth direction, the mobility of the PMOS transistors is improved.

SRAM formed on SOI substrate

Integrated circuit contact structures are fabricated by forming a first layer comprising niobium (Nb) on a silicon substrate and forming a second layer comprising a near noble metal on the first layer, opposite the silicon substrate. The near noble metal, also referred to as a Group VIII metal, is preferably cobalt (Co). The near noble metal has higher diffusion coefficient than the niobium and the silicon substrate. Annealing is then performed to diffuse at least some of the near noble metal through the first layer and react the diffused near noble metal with the silicon substrate to form a third layer comprising a near noble metal silicide, and to form a fourth layer comprising niobium-near noble metal alloy on the third layer. It has been found that the use of niobium can reduce substrate consumption compared to conventional cobalt titanium double-metal silicide fabrication processes. The annealing step is preferably performed in a nitrogen containing ambient to also form a fifth layer comprising niobium nitride on the fourth layer, opposite the third layer. Moreover, when a native oxide layer is included on the silicon substrate, the annealing step can react the niobium with the native oxide and thereby remove the native oxide layer.

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Seoul, South Korea

Young-Wug Kim