Samsung Electronics Co., Ltd.

Young-wug Kim

Byung-Sun Kim

Young-Gun Ko

Hee-Sung Kang

Sung-bae Park

Jeong-hwan Yang

Kwang-dong Yoo

Seok-kyun Jung

Min-Su Kim

Nae-in Lee

Moon-han Park

Kyung-Tae Lee

Jun Hui Kim

Min-su Kim

Kwang-Il Kim

Kwang-il Kim

Chang-bong Oh

Hee-sung Kang

Kwan-young Oh

Eun-Han Kim

Sung-Dae Park

A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Metal oxide semiconductor field effect transistor for reducing resistance between source and drain and method for fabricating the same

An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.

SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same

A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same

The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P&minus; or N&minus; layer respectively surrounds a P&plus; or N&plus; layer), in other words, only onto a high density of impurity layer, the P&plus; or N&plus; layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

Semiconductor device having silicon on insulator and fabricating method therefor

An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions. The plurality of dummy conductive regions are formed on the node regions of the lattice-shaped isolation region. In another embodiment, an array of isolation regions is formed, defining a lattice-shaped dummy active region. An array of dummy conductive regions is formed on the array of isolation regions. Related integrated circuit devices are also described.

Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions

Metal oxide semiconductor field effect transistor for reducing resistance between source and drain

A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

A method of forming damascene wiring without dishing and erosion employs a dummy layer to slow or delay polishing in selected regions and thereby prevent dishing and erosion of the damascene wiring. The dummy layer is above wide damascene regions and areas containing closely packed damascene regions. Therefore, non-uniform sheet resistance of the damascene metal wiring and electro-migration due to an increase in the local current density of the metal wiring can be prevented.

Method of fabricating damascene metal wiring

Integrated circuit devices including distributed and isolated dummy conductive regions

A method of manufacturing a capacitor whose top and bottom electrodes have the nearly equal doping concentrations. In the method, a top surface of the capacitor top electrode is polished by a CMP (chemical mechanical polishing) and then doped using the same doping process as the capacitor bottom electrode, so that other elements can be isolated during the doping process. After forming the capacitor bottom electrode, thermal oxidation is performed so that the injected impurity ions of the capacitor bottom electrode are segregated toward a top surface portion thereof. With this method, a doping concentration at the top surface portion of the capacitor bottom electrode becomes higher than that at other portions thereof, and thereby the capacitor top and bottom electrodes may have a nearly same doping concentration at the interface therebetween.

Method of manufacturing capacitor for analog function

A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.

Growing community of inventors

Suwon, South Korea

Young-wug Kim