Samsung Electronics Co., Ltd.

Hyundai Motor Company

Young-Wook Park

Seok-Jun Won

Young-Min Kim

Seung-Hwan Lee

Han-Mei Choi

Young-Sun Kim

Jae-Jong Han

Young-Dae Kim

Kyung-hoon Kim

Kyoung-Seok Kim

Se-Jin Shim

Sang-Hyeop Lee

Eun-Taek Yim

You-Chan Jin

Ju-Tae Moon

Kab-Jin Nam

In-Sung Park

Jae-Hyun Yeo

Byeong-Yun Nam

Hyoung-Joon Kim

Jin-Gi Hong

Won-Jin Kim

Jeong-Do Ryu

Jung-Hun Seo

Un-Koo Lee

Ki-Chul Kim

Kyung-Wan Nam

Myeong-Jin Kim

Dong-Jo Kang

Ji-Sang Yahng

Sang-Ho Lee

Beung-Keun Lee

Tae-Gon Park

Hyung-Bae Jang

Jum-Soo Chang

A layer deposition method includes: feeding a reactant with a first flow of an inert gas as a carrier gas into a reaction chamber to chemisorb the reactant on a substrate; feeding the first flow of the inert gas to purge the reaction chamber and a first reactant feed line; and feeding the second flow of the inert gas into the reaction chamber through a feed line different from the first reactant feed line.

Layer deposition methods

In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

Method of forming a layer on a semiconductor substrate

A layer is formed on a semiconductor wafer in an apparatus having a processing chamber, a transferring chamber, and a wafer boat. The boat having the semiconductor wafer thereon is rotated in the transferring chamber. While the boat is rotated, the boat is transferred between the transferring chamber and the processing chamber and a reaction gas is provided to the processing chamber to form the layer on the wafer.

Method of forming a layer on a wafer

The present invention relates to a cryptographic apparatus for encrypting data stored in a memory. The cryptographic apparatus of the present invention operates in the ECB, CBC, CBC-MAC, counter and OCB modes using small and simple elements. The cryptographic apparatus minimizes data communication between CPU and the cryptographic apparatus to improve the performance of the communication system. On the other hand, the input buffer and output buffer of the cryptographic apparatus are configured to store at least two blocks respectively, so that the performance of the cryptographic apparatus is maximized. Furthermore, the cryptographic apparatus supports zero-padding, so that the process of the CPU is minimized.

Cryptographic apparatus for supporting multiple modes

Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

Methods of fabricating a semiconductor substrate for reducing wafer warpage

In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

Methods and apparatus for forming thin films for semiconductor devices

A knuckle is minimized in size to be located in an internal space of a rear wheel. An upper arm is disposed lower than a conventional double wishbone type and one end of the upper arm is secured to the knuckle. A shock absorber couples at a lower end thereof to the knuckle by passing through a space between a lower arm and assist arm. This configuration thus constructed greatly increases the space of the trunk room, reduces noise by minimizing the transmission of road impact and vibration, and improves ride comfort as well as braking stability and turn stability.

Multi-link rear suspension system

Disclosed are a method for cleaning a deposition chamber by removing attached metal oxides, and a deposition apparatus for performing in situ cleaning. A first gas and a second gas are provided into the deposition chamber. The first gas is reacted with metal included in the metal oxide to generate reacting residues. The second gas then decomposes the reacting residues, and the decomposed residues are exhausted out of the chamber. Thus, this cleaning process can be rapidly accomplished while the deposition chamber is not opened or separated from a deposition apparatus.

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Provided is a method for manufacturing semiconductor devices including channel trenches that are separated by isolation structures. According to the process, the substrate is etched to form isolation trenches after which a sidewall oxide layer, a liner nitride layer and a field oxide layer are subsequently formed on the substrate and in the isolation trenches. The substrate is then planarized to remove upper portions of the sidewall oxide layer, the liner nitride layer and the field oxide layer to expose surface portions of the substrate between adjacent isolation trench structures. Channel trenches are then formed in the exposed surface portions of the substrate leaving residual substrate regions adjacent the isolation trench structures. These residual substrate regions are then oxidized and removed to form improved second channel trenches for the formation of transistor regions.

Method for manufacturing a semiconductor device

Disclosed is a method for forming a multi-layered structure having at least two films on a semiconductor substrate. The substrate is disposed on a thermally conductible stage for supporting the substrate. After the distance between the stage and the substrate is adjusted to a first interval so that the substrate has a first temperature by heat transferred from the stage, a first thin film is formed on the substrate at the first temperature. The distance is then adjusted from the first interval to a second interval so that the substrate reaches a second temperature, and then a second thin film is formed on the first thin film at the second temperature, thereby forming the multi-layered structure on the substrate. The multi-layered structure can be employed for a gate insulation film or the dielectric film of a capacitor.

Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure

The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Methods of fabricating integrated circuit devices providing improved short prevention

Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Integrated circuit capacitors having doped HSG electrodes

Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &#x3bc;&#x3a9;&#x2022;cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.

Growing community of inventors

Gyeonggi-do, South Korea

Young-Wook Park