Samsung Electronics Co., Ltd.

Hyundai Motor Company

Young-wook Park

Young-sun Kim

Seung-Hwan Lee

Yeong-kwan Kim

Seok-Jun Won

Cha-young Yoo

Dong-Chan Kim

In-Sung Park

Cha-Young Yoo

Seung-hee Nam

Kab-jin Nam

Sung-Tae Kim

Ki-yeon Park

Yong-woo Hyung

Nae-in Lee

Ki-chul Kim

Ki-Hyun Hwang

Han-Mei Choi

Jae-Young Park

Young-Sun Kim

Kyung-hoon Kim

In-Seak Hwang

Jung-Hwan Oh

Heung-soo Park

Se-Jin Shim

Kyung-hun Kim

Bong-young Yoo

Moon-yong Lee

Dae-Hong Ko

Sang-jeong Oh

Se-jin Shim

Kyoung-Hoon Kim

Sang-in Lee

Hee-Sook Park

Jong-myeong Lee

Chang-seok Kang

Jae-Soon Lim

Hong-bae Park

Yun-Jung Lee

Kong-Soo Lee

Jae-Jong Han

Jin-Su Lee

Hyun-jung Lee

Young-kuk Kim

Kyoung-Seok Kim

Jeon-Il Lee

Seung-Mok Shin

Doo-sup Hwang

Sang-Hyeop Lee

Soon-yeon Park

Kwan-young Oh

Sung-Eui Kim

Sung-Je Choi

Min-woo Kim

Mikio Takagi

Hee-don Hwang

Dong-Bok Lee

Gi-Hyun Hwang

Sun-woo Kwak

Duk-soo Yoon

Yoo-jin Jeong

Mun-han Park

Dae-rok Bae

A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.

Method of manufacturing integrated circuit device

Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Methods of manufacturing semiconductor devices

Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Method for fabricating semiconductor device horizontally shifted contact plug pattern

A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.

Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same

A method for forming a film includes forming the film on a substrate, followed by performing a first annealing of the film at a temperature lower than a crystallization temperature of the film. A second annealing of the film is performed at a temperature higher that the crystallization temperature. Forming the film and the first annealing of the film are performed in situ in a chamber. Alternatively, the first and second annealing are performed in situ in an apparatus.

Method for forming a thin film

The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-SiGeconductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.

[object Object]

A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and Ogas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Method of forming a metal oxide film

An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

One-cylinder stack capacitor and method for fabricating the same

The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si Ge conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.

Integrated circuit devices that utilize doped Poly-Si1&minus;xGex conductive plugs as interconnects

Method of forming a thin film using atomic layer deposition

Methods and apparatus for plasma annealing layers of a microelectronic capacitor on a substrate are provided to improve the leakage current characteristics of a capacitor and/or to reduce the number of impurities in an electrode.

Methods for forming capacitors on semiconductor substrates

A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

Method of manufacturing a semiconductor device including alignment mark

Methods of forming Ta O layers in a process chamber are disclosed. A Ta O layer can be maintained at a first temperature that is less than a temperature for crystallization of the Ta O layer. At least one of a position of the Ta O layer in the process chamber relative to the heater and a pressure in the process chamber is changed to increase the temperature of the Ta O layer to about the temperature for crystallization.

Methods of fabricating capacitors including Ta2O5 layers in a chamber including changing a Ta2O5 layer to heater separation or chamber pressure

Growing community of inventors

Suwon, South Korea

Young-wook Park