Samsung Electronics Co., Ltd.

Young-Woo Park

Jae-Duk Lee

Jung-Dal Choi

Jae-Goo Lee

Jin-taek Park

Jang-Hyun You

Dong-Sik Lee

Jee-Hoon Han

Chang-seok Kang

Tae-Yong Kim

Kohji Kanamori

Jong-Sun Sel

Sung-Il Chang

Byung-Kwan You

Jong-won Kim

Dong-Hwa Kwak

Jin-Taek Park

Jong-Hoon Na

Chang-Hyun Lee

Sung-Hoi Hur

Su-Jin Park

Jae-Sung Sim

Shin-Hwan Kang

Jung-hoon Park

Sang-Ick Joo

Sang-yong Park

Won-Sung Lee

Jong-Min Lee

Yong-Hoon Son

Kyung-Hyun Kim

Jun Hyuk Seo

Kye-Hyun Kyung

Jung-dal Choi

Ju-Hyung Kim

Kwang-Soo Seol

Woo-Sik Kim

Yong-chul Oh

Jin-Soo Lim

Chang Hyun Lee

Young-Hwan Son

Chul Bum Kim

Phil-Ouk Nam

Jong-Heui Song

Yeon-Sil Sohn

Chung-Il Hyun

Yoo-cheol Shin

Jin-I Lee

Won-Bong Jung

Byung-Kyu Cho

Kwang-Chul Park

Cheon-An Lee

Do-hyun Lee

Kanamori Kohji

Moo-Rym Choi

Byeong-Ju Kim

Chung-Jin Kim

Yung-hwan Son

Chang-Shik Choi

A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.

Semiconductor package including shielding cover that covers molded body

Fabrication method of semiconductor package including shielding wall and cover

A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

Methods of manufacturing vertical memory devices

Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.

Semiconductor devices with vertical channel structures

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

Non-volatile memory device

Vertical memory devices and methods of manufacturing the same

A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

Semiconductor devices

A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Nonvolatile memory device and a method for fabricating the same

A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

Non-volatile memory device having vertical structure and method of manufacturing the same

A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

Vertical semiconductor device

A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming a channel hole by etching the insulating layers and the sacrificial layers to expose a partial region of the substrate, forming a channel structure in the channel hole, forming an opening by etching the insulating layers and the sacrificial layers to exposed a portion of the substrate, forming a plurality of side openings that include first side openings and a second side opening by removing the sacrificial layers through the opening, forming gate electrodes to fill the first side openings, and forming a blocking layer to fill the second side opening.

Method of fabricating memory device

The present invention is directed to a photographing lens containing, in order from an object side: a first lens having a positive refractive power and a convex surface facing the object side; a second lens having a negative refractive power; a third lens having a positive refractive power; and a fourth lens having a negative refractive power and at least one aspheric surface, the photographing lens satisfying the following conditional expressions: where Ldenotes the distance on the optical axis between the object side of the first lens and the image side of the fourth lens; f denotes the total focal length of the photographing lens; and fdenotes the focal length of the third lens.

Photographing lens

A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

Semiconductor device having vertical channel and air gap, and method of manufacturing thereof

Growing community of inventors

Seoul, South Korea

Young-Woo Park