Pitney Bowes Inc.

Young W Lee

Arno Muller

Sungwon R Moh

Michael J Lorello

Maria P Parkos

Edward R Bass

George J Doutney

Thomas F Barraza

A mailing machine base includes a docking system for a User Interface Controller (UIC) that provides a feedback signal to the mailing machine based on the presence of the UIC. When the UIC is inserted into a docking connector of the mailing machine, the mailing machine detects the presence of the UIC. A delay circuit within the mailing machine provides a signal to a power control circuit after a predetermined time delay. The power control circuit, based on the signal from the delay circuit, will provide power to the UIC only after the UIC has been securely docked for the full predetermined time delay. When the UIC is removed from the mailing machine, the mailing machine, based on the feedback signal, will quickly remove the power provided to the docking connector. Thus, the mailing machine can remain powered during removal and replacement of the UIC.

Auto power-on, hot-pluggable user interface controller for mailing machines

A mailing machine that includes a docking system for the User Interface Controller (UIC) that provides a safety interlock to protect the user from accessing potentially hazardous voltages when the UIC is removed is provided. A docking board provides a connection between the mailing machine and the UIC. The UIC mates with a docking connector on the docking board. Potentially hazardous signal levels pass through a relay on the docking board to the docking connector. A supply voltage for the relay's coil passes through docking board to the UIC and back to the relay on the docking board. If the UIC is removed, the supply voltage for the relay's coil will be removed, causing the relay to open and preventing any of the potentially hazardous signals from being transmitted to the docking connector on the docking board.

Mailing machine having a user interface controller safety interlock to provide protection from hazardous voltages

An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor. Respective ones of the control signals are the memory write enable signals for write enabling the first or second units where write enable signals are directed to the respective memory unit. The control system further maintains the respective write enable control signals active for at least the write access time of the first memory unit in response to generation of a respective one of the write enable control signals by the address decoder. The control system further maintains the respective write enable control signal active for an additional second period such that sum period of the first period of time in combination with the second period of time is at generally equal to the write access time required by the second memory unit.

Address decoder with memory wait state circuit

The memory access limiting circuit detects when two or more of memory units associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit. The integrated circuit also includes an address decoding for receiving the unique address signal and causing a write enable signal to be generated for the memory units and one of a plurality chip select signals to be generated for a respective one of the memory units. The monitoring circuit monitors the pin levels of the integrated circuit assigned for enabling the respective memory unit. The monitoring circuit generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor for corrective action.

Multi-memory access limiting circuit for a multi-memory device

The memory security circuit detects when a memory unit has been accessed independently of an address instruction of a programmable microprocessor. The microprocessor is programmed to provide a unique address signal for write enabling a discrete memory unit. The memory unit has a write enable pin and chip select pin which when enabled in combination permits writing into the memory unit. The address decoder receives the unique address instruction and causes a write enable signal and a chip select signal to be generated for that memory unit. The write enable signal and chip select signal are to be received, respectively, by the write enable pin and the chip select pin of the memory unit. The memory security circuit monitors the write enable pin and the chip select pin of the memory unit and generates a first output signal when the memory unit has been properly addressed. A second output signal is generated when the memory unit has not been addressed by the address decoder and the write enable and the chip select signals are present at the memory unit.

Memory monitoring circuit for detecting unauthorized memory access

The printer control module is programmed to output control signals to the printer driver characterized by the data written in the control registers. The control system for a printing apparatus includes a printer unit responsive to a printer driver unit. The printer driver unit is responsive to the control system. The control system has a programmable printer control module in communication with the printer driver unit and a programmable microcomputer in bus communication with the printer control module. The microcomputer has a non-volatile memory unit for storing the data. The printer driver unit is responsive to control signals from the printer control module for driving the printer unit. The printer control module includes a buffer for holding printer data and the registers of the control module, including a control register, a shift register and a strobe width register. A strobe signal module generates a strobe signal for the printer driver unit having one of a plurality of strobe widths selected in response to the data written in the strobe width register. The control module also selectively causes one of a plurality of clock signals for the printer driver unit in response to data written in the control register. A shift module causes printer data to be delivered to the printer driver unit in one of a plurality of frame sizes in response to data written in the shift register. The programmable microcomputer is programmed to writing data into the control registers.

Control system for an electronic postage meter having a programmable

A micro control system includes a programmable microcontroller which is in bus communication with memory units and a operating power supply for providing operating power to said microcontroller. A communication module is part of the micro control system and is in communication with the data bus of the micro control system for receiving and transmitting data messages to an external device, and for encoding said transmitted data messages to conform to a serial communication protocol and decoding said received data messages. The microcontroller is programmed to generated a first control signal or a second control signal. An input-output interface is included as part of the micro control system and includes a number of switching units responsive to the first control signal of the microcontroller to place the respective switching units in a first mode of operation for providing communication between said communication module and a connector. The switching units also respond to said second control signal from the microcontroller to place said switching units in a second mode of operation for providing communication between said data bus of the micro control system and said connector to which connector the external device is attached.

Digital communication I/O port

The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.

Data encryption control system

The control system controls the operation of a charge coupled device. The operation of the charge coupled device is responsive to a shift clock signal of a given frequency and a shift enable signal. The control system includes a timer for generating one of a number of shift clock signals. Each of the shift clock signals has a different frequency. A programmable register stores a plurality of control bits which may be programmed into the program memory of the control system. A multiplex switching is used for selecting one of the shift clock signals in response to the state of the control bits and directing the selected shift clock signal to the charge coupled device. An address decoder in response to addressing by the microprocessor, generates the shift enable signal which signal is directed to the charge coupled device concurrently with the presence of the selected shift clock signal.

Charge coupled device control module

The method for preventing monitoring of postage indicia data which is sent from a postage metering vault to a remotely located digital printer over a communication link between the meter vault and the digital printer. The meter is provided with an encryption engine for encrypting postage indicia data utilizing a encryption key. The digital printer includes a decryption engine for decrypting postage data received from said meter utilizing the same encryption key and then prints a postage indicia pursuant to the decrypted postage indicia data. The postage meter also includes a key manager for generating new encryption key pursuant to a token which is either randomly generated or generated pursuant to an algorithm by a similar encryption key manager located in the digital printer which token is also used to generate the decryption key for the decryption engine. As a result, the encryption keys are the same. Upon power-up of the system or at such other preselected times, the print controller module of the digital printer sends out an encrypted message to the meter. The message consist of a random number. The encryption/decryption engine of the vault decrypts the message. The vault then returns an encrypted new message to the print controller which includes an encoded representation of the relationship of the two messages. Upon receiving the new message from the vault, the print controller decrypts the new message and verifies the relationship. The print controller is then enabled to print a postage indicia.

Method for identifying a metering accounting vault to digital printer

The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting medium having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for generating one of a plurality of timing signals in accordance with timer data. Also included are a plurality of non-volatile memory units. The non-volatile memory unit responsive to other ones of the control signals from the address decoding module to enable the non-volatile memory units for writing data into the non-volatile memory unit by the microprocessor. The integrated circuit further includes a non-volatile memory access timer unit for causing the control signal from the address decoding module enabling the non-volatile memory units to stay active for a predetermined time of the non-volatile memory access timer.

Control system for an electronic pastage meter having a programmable

The micro-controller system is comprised of a programmable microprocessor, a plurality of memory units having a plurality of addressable memory registers. The memory units are in bus communication with the programmable processor and an application specific integrated circuit. The application specific integrated circuit includes a circuit for dividing the memory units into a plurality of addressable regions in response to programming of the programmable microprocessor. The microprocessor is programmed such that the initial address for each of the regions is assigned by the most significant address bits, and the uppermost address for the region being programmably defined by an uppermost address for the respective region. The circuit includes a plurality of addressable registers. The microprocessor can address each of the circuit registers and write a respective uppermost address in a respective one of the registers, the respective address corresponding to uppermost addressable registers of the respective addressable regions of the memory units.

Address decoder with memory allocation for a micro-controller system

The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting means having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module means for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for generating one of a plurality of timing signal in accordance with timer data. The data also includes motor data. Prime motor register units are responsive to other ones of the control signals from the address decoding module to enable writing of the motor data into the timer registers by the microprocessor. A motor control unit is responsive to the motor data for generating a plurality of motor control signals in accordance with the motor data.

Programmable clock module for postage metering control system

A programmable timer circuit which is integrated into an application specific integrated circuit includes a programmable timer counter. The programmable timer counter receives count data which is written to registers of the integrated circuit and is caused to initiate a count until that count is reached in response to clock signal. A programmable microprocessor is provided for controlling the programmable timer circuit and reading count data and mode data from non-volatile memory units in response to the microprocessor's programming and writing the count data and mode data into the registers of the application specific integrated circuit. In response to the mode data the programmable timer circuit assumes either a one shot mode or a continuos mode when the programmable timer.

Dual mode timer-counter

A programmable timer circuit is comprised of a programmable timer counter for receiving a count and for counting to the count. A clock signal for driving the timer counter which timer counter generates a signal representative of the count. A microprocessor generates count data in response to programming of the microprocessor. Timer data register receive the count from microprocessor. A first gate is provided having an enabled mode and an non-enabled mode for enabling loading of the timer data from the timer data register to the timer counter input only in the enabled mode. A monitoring circuit is provided for monitoring the timer count and enabling the gate mean to the enabled mode only when the timer has time-out.

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Orange, CT, United States of America

Young W Lee