Samsung Electronics Co., Ltd.

Young-Uk Oh

Dae-Young Kim

Min-joong Rim

A combinational logic type inversion circuit for calculating the inverse of an arbitrary element .alpha..sup.i in a finite field, includes a power and multiplication circuit for calculating a primitive element .alpha..sup.i raised to the (2.sup.1)-th power through a primitive element .alpha..sup.i raised to the (2.sup.m-1)-th power and multiplying all of the primitive elements .alpha..sup.i raised to the (2.sup.1)-th power through .alpha..sup.i raised to the (2.sup.m-1)-th power together to generate an output M.sub.OUT, and a divider circuit for dividing the output M.sub.OUT of the power and multiplication circuit by the primitive element .alpha. raised to the (2.sup.m -1)-th power.

Circuit for calculating the inverse of an arbitrary element of a finite

The present invention relates to a circuit for calculating an ELP and an EEP, and a Reed-Solomon decoder using the same. The circuit includes: first storage device for storing a syndrome value, coefficient values of the ELP, a discrepancy value and the size of a shortened code; second storage device for storing the coefficient values of the ELP, the reciprocal value of the discrepancy, the discrepancy value, the coefficient values of the ELP and the values obtained by differentiating the coefficient values of the ELP; first selecting device for selectively outputting the values stored in the first storage device in response to first to sixth control signals; second selecting device for selectively outputting the values stored in the second storage device in response to the control signals; multiplication device for multiplying the values selected by the first and second selecting means; third selecting means for selectively outputting the resultant values multiplied by the multiplication device in response to the control signals; third storage device for storing the resultant values selectively output by said third selecting device. Accordingly, the construction of the circuit becomes simple and a chip area can be reduced at the time of integration.

Circuit of calculating errata locator and evaluator polynomial,

A traceback-performing apparatus includes a first storing portion which receives and stores new path metric values and minimum path metric value so that the first input value is output later and the later input value is output first. A first trace logic portion which receives outputs of the first storing portion and the minimum path metric value and generates a first state which is the next state to be traced. A second storing portion which receives and stores the output of the first storing portion so that the first input value is output first and the later input value is output later. A second trace logic portion which receives the output of the second storing portion and the first state and generates a second state which is the next state to be traced. And, a third storing portion which receives and stores the second state so that the first input value is output later and the later input value is output first so as to find the decoded bits. Therefore, cost is saved in embodying the Viterbi decoder in a VLSI by reducing the required chip area, simplifying address-generation and eliminating the need for global interconnection.

Traceback-performing apparatus in viterbi decoder

In a decoding system which decodes a transmitted signal encoded by using a Reed-Solomon code, an error locator polynomial of the nth iteration is calculated based on a predetermined number of syndrome values; a group of variables of the (n-1)st iteration including a discrepancy and an error locator polynomial thereof; and an error locator polynomial of the (n-2)nd iteration. The method for providing the error locator polynomial comprises the steps of calculating a discrepancy of the nth iteration based on the syndrome values and the error locator polynomial of the (n-1)st iteration; calculating a temporal term based on the discrepancy of the (n-1)st iteration and the error locator polynomial of the (n-2)nd iteration; determining a correction term based on the temporal term and the discrepancy of the nth iteration; and computing the error locator polynomial of the nth iteration based on the correction term and the error locator polynomial of the (n-1)st iteration.

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Incheon, South Korea

Young-Uk Oh