Lsi Corporation

Marvell International Limited

Netapp, Inc.

Young-Ta Wu

Siamack Nemazie

Shiang-Jyh Chang

Andrew Hyonil Chong

Fei Sun

Tony Yoon

Wei Xu

Sam Nemazie

Jinjin He

Ka-Ming Keung

Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.

Method and apparatus for compressing LUT

An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Switching serial advanced technology attachment (SATA) to a parallel interface

An embodiment of the present invention is disclosed to include a hard disk drive allowing for access by two hosts to a device. Further disclosed are embodiments for reducing the delay and complexity of the SATA disk drive.

Dual port serial advanced technology attachment (SATA) disk drive

Route aware serial advanced technology attachment (SATA) switch

An embodiment of the present invention is disclosed to include a fiber channel target device for receiving information in the form of frames and including a controller device coupled to a microprocessor for processing the frames received from the host, at least one receive buffer for storing the frames and having a buffer size, the controller device issuing credit to the host for receipt of further frames in a manner wherein only one microprocessor is needed to process the frames while maintaining a buffer size that is as small as the number of first type of frames that can be received by the fiber channel target device from the host.

High performance architecture for fiber channel targets and target bridges

An embodiment of the present invention includes a switch employed in a system having two hosts and a device and for coupling two or more host ports to a device. The switch includes a power signal control circuit generating a power signal for use by the device in receiving power for operability thereto, the power signal control circuit responsive to detection of inoperability of the device and in response thereto, toggling the power signal to the device while avoiding interruption to the system.

Serial advanced technology attachment (SATA) switch that toggles with power control to hard disk drive while avolding interruption to system

A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

Growing community of inventors

Fremont, CA, United States of America

Young-Ta Wu