Samsung Electronics Co., Ltd.

Young-Sun Min

Nam-Jong Kim

Jong-Hyun Choi

Jong-hyun Choi

Kyu-Chan Lee

Chul-Woo Yi

Jung-Bae Lee

Chul-Woo Park

Ki-Seok Oh

Dong-Il Seo

Jae-Youn Youn

Sang-Hoon Jung

Chang-ho Shin

Jong-Eon Lee

A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

Layout structure of bit line sense amplifiers for a semiconductor memory device

A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal.

Semiconductor memory device and method of controlling sense amplifier of semiconductor memory device

A circuit and method for generating an internal power supply voltage are disclosed. The circuit includes an internal power supply voltage pre-processing unit configured to generate a first internal power supply voltage in response to an external power supply voltage in a power-up mode and a deep power-down (DPD) exit mode to provide the first internal power supply voltage to an output node, and further configured to define a transition time for the first internal power supply voltage, an internal power supply voltage generating unit configured to generate a stable second internal power supply voltage in response to the external power supply voltage to provide the second internal power supply voltage to the output node, and an initialization signal generating unit configured to generate an internal initialization signal in response to the first internal power supply voltage and the second internal power supply voltage.

Circuit and method for generating an internal power supply voltage

An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.

Internal source voltage generating circuit of semiconductor memory device

A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter a deep-power-down (DPD) mode without generating the first initialization signal. The first initialization signal may be generated if the semiconductor memory device exits the DPD mode.

Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same

In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have different voltage levels. An output voltage generator generates a plurality of output voltages by independently driving each of the plurality of external source voltages in response to a corresponding one of the plurality of reset signals. The output voltage generator outputs the plurality of output voltages through a common output terminal.

Voltage generating circuits for semiconductor memory devices and methods for the same

A circuit and method of driving a sub-word line of a semiconductor memory device capable of reducing power consumption is disclosed. The sub-word line driving circuit includes a first transistor, a second transistor and a third transistor. The first transistor pre-charges a boost node to a first voltage in response to a main word line driving signal. The second transistor boosts the boost node to a second voltage in response to a sub-word line driving signal, and provides the sub-word line driving signal to a sub-word line. The third transistor provides the main word line driving signal to the sub-word line in response to a third voltage that has a lower level than a logic 'high' state of the sub-word line driving signal.

Circuit and method of driving sub-word lines of a semiconductor memory device

A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.

DRAM and method for partially refreshing memory cell array

A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

Methods and circuits for programming addresses of failed memory cells in a memory device

A verifying circuit and a method of repairing a semiconductor device, the verifying circuit of example embodiments may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on a control signal and an output signal from the first fuse circuit, and a second fuse circuit configured to test whether a plurality of second fuses are programmed based on the test signal.

Verifying circuit and method of repairing semiconductor device

An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.

Anti-fuse circuit and anti-fusing method

A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc&#x3e;Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIand VI, where VI&#x3e;VI; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOand VO, where VO&#x3e;VO, wherein VI&#x3e;VOor VI&#x3c;VO, and wherein VO&#x3e;Vcc and VO&#x3c;Vss.

Level shifter with low leakage current

A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.

Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature

A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.

Growing community of inventors

Seoul, South Korea

Young-Sun Min